Kampi/OV7670

FPGA interface and driver for an OV7670 camera sensor.

Language: VHDL - Size: 31.3 KB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1

ultraembedded/core_jpeg

High throughput JPEG decoder in Verilog for FPGA

Language: Verilog - Size: 171 KB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 221 - Forks: 43

KastnerRG/cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Language: SystemVerilog - Size: 12.4 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 72 - Forks: 10

riyasach189/Vitis_HLS_2022.1_Examples

This is a collection of some examples designed in the Vivado Design Suite.

Language: Tcl - Size: 1.18 MB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

DOUDIU/AXIS-AXI4-AXIS

This project is designed to delay the output of the video stream in AXI-STREAM format.

Language: Verilog - Size: 151 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 5 - Forks: 0

pkill37/asic-linreg

ASIC for executing vectorized gradient descent on linear regression problems.

Language: VHDL - Size: 110 MB - Last synced at: 12 months ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1

2uger/petalinux_notes

Language: SystemVerilog - Size: 10.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

mnemocron/axis-skidbuffer Fork of amamory/axis-skidbuffer

A one-position buffer compatible with AXI Stream interface

Language: VHDL - Size: 668 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

amamory/axis-skidbuffer-lfsr

An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals

Language: Tcl - Size: 102 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

mnemocron/axi-perf-counter-pattern

Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.

Language: VHDL - Size: 856 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

amamory/axis-protocol-checker

AXI stream protocol checking design

Language: Tcl - Size: 86.9 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

alknvl/axis_udp

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

Language: Verilog - Size: 137 KB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 12

amamory/axis-skidbuffer

A one-position buffer compatible with AXI Stream interface

Language: Tcl - Size: 16.6 KB - Last synced at: about 1 month ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 1

MasterPlayer/axis_uart_bridge

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

Language: SystemVerilog - Size: 6.84 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

fcayci/vhdl-axis-uart

UART to AXI Stream interface written in VHDL

Language: VHDL - Size: 27.3 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 12 - Forks: 3

MasterPlayer/adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

Language: C - Size: 2.23 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

gururavi/rtl

Synchronous and Asynchronous FIFO with AXI interface

Language: SystemVerilog - Size: 9.77 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

amamory/axi_noc_counter_ip

A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source

Language: Tcl - Size: 32.2 KB - Last synced at: about 1 month ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

amamory/zynq-ps-hermes-noc

Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface

Language: Tcl - Size: 990 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

amamory/hermes-2x2-noc-axis-ip

A 2x2 mesh NoC compatible with AXI streaming interface

Language: Coq - Size: 34.2 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

amamory/skidbuffer-testing

vivado design to test the skidbuffer IP

Language: Tcl - Size: 85.9 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

amamory/zynq-hermes-noc-demo

A demonstrator of Hermes network-on-chip communicating with the ARM processor

Language: Tcl - Size: 74.2 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 2

loykylewong/bwa-mem-fpga

Fast bwa-mem dna matching algor implemented in system verilog, fully synthesizable.

Language: Stata - Size: 9.24 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

catarinaacsilva/vivado-xilinx-tutorials

Tutorials or projects example to use Vivado 2019.2 and Vitis

Language: VHDL - Size: 338 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 1