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GitHub topics: uart-rx

sushi0706/uart

verilog-uart

Language: Verilog - Size: 359 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

0marAmr/UART-Interface

Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL

Language: Verilog - Size: 1.31 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Martan03/INC-UART_RX

First project for the INC subject

Language: VHDL - Size: 1.19 MB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

MasterPlayer/axis_uart_bridge

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

Language: SystemVerilog - Size: 6.84 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

FunPythonEC/xl320_upy

Dynamixel xl320 support for ESP boards with micropython.

Language: Python - Size: 33.2 KB - Last synced at: about 2 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 1

Related Keywords
uart-rx 5 uart-tx 4 uart 3 uart-verilog 2 xl-320 1 serial-packet 1 robotics 1 micropython-esp8266 1 micropython-esp32 1 dynamixel-servos 1 bytearray 1 zynq 1 xilinx 1 systemverilog 1 fpga 1 axi-stream 1 artix 1 vhdl 1 receiver 1 logisim 1 uart-interface 1 digital-design 1 communication-interface 1 verilog 1 uart-protocol 1 modelsim 1