GitHub / 0marAmr / UART-Interface

Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL

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PURL: pkg:github/0marAmr/UART-Interface

Stars: 0
Forks: 0
Open issues: 0

License: None
Language: Verilog
Size: 1.31 MB
Dependencies parsed at: Pending

Created at: almost 2 years ago
Updated at: over 1 year ago
Pushed at: over 1 year ago
Last synced at: over 1 year ago

Topics: communication-interface, digital-design, uart-interface, uart-rx, uart-tx, uart-verilog

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