GitHub topics: xilinx-vivado | Ecosyste.ms: Repos

acageduser/DMA-Attack-Firmware-Customization

This cybersecurity guide provides a comprehensive approach to hardware obfuscation using LambdaConcept's PCIe Screamer Squirrel DMA board. It is intended for educational and research purposes only.

Size: 96.7 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 128 - Forks: 18

Yanxiang-ZHU/Whack-a-Mole-GameMachine

This is the individual class project for ASIC2025, building the game machine based on FPGA(Xilinx Artix7 XC7A200T), with topdown design flow.

Language: VHDL - Size: 165 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

LuisMLopez-dev/Double-Dabble-Algorithm

This is a VHDL code for converting a binary number to a BCD (binary-coded decimal) number using the Double Dabble Algorithm.

Language: VHDL - Size: 10.7 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

SKpro-glitch/Multi-Bit-Comparator

Variations of a multi-bit generalized magnitude comparator for different area and timing.

Language: D - Size: 252 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

SKpro-glitch/Parallel_Multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 2 - Forks: 0

Soumyajit7819/Verilog-Spi-Master

SPI master have been implemented using Verilog in Xilinx Vivado

Language: JavaScript - Size: 591 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 1 - Forks: 0

Madhu-Krishnan-A-P/pattern-detector

SystemVerilog implementations of a 101 pattern detector using both structural and behavioral modeling styles. Includes separate testbenches for each implementation. Designed for detecting overlapping 101 patterns in a serial bitstream, useful for learning FSM design and simulation in digital systems.

Language: SystemVerilog - Size: 190 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 0 - Forks: 0

Madhu-Krishnan-A-P/binary-gray-converter

SystemVerilog implementation of a Binary to Gray Code Converter in both structural and behavioral styles. Includes a simple testbench for verification. Useful for digital design learners and FPGA developers.

Language: SystemVerilog - Size: 222 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 0 - Forks: 0

Madhu-Krishnan-A-P/mux

This repository contains the Verilog design and testbench for a 4x1 Multiplexer. It uses two select lines to choose one of the four inputs (A0–A3) and drive it to a single output based on the logic expression: Y = S1’S0’A0 + S1’S0A1 + S1S0’A2 + S1S0A3

Language: Verilog - Size: 2.93 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

SUHANI102003/SYNCHRONOUS-FIFO

This repo contains system verilog codes for synchronous fifo design and its verification using self-checking testbench and class based verification.

Language: SystemVerilog - Size: 108 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

avnlk/radix2-fft-using-dsp48-on-fpga

This project implements the Radix-2 Fast Fourier Transform (FFT) algorithm on an FPGA using Xilinx DSP48 IP blocks. The design leverages the parallel processing capabilities of FPGAs to achieve high performance in signal processing tasks.

Language: Jupyter Notebook - Size: 13 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 2

ItzzInfinity/100-days-of-RTL

Trying to get a new skill

Language: Verilog - Size: 79.5 MB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 23 - Forks: 6

Un2versidad/Digital-Logic

Introduction to VHDL and Digital Logic - Basys 3 and Vivado Projects Repository

Language: Tcl - Size: 2.02 MB - Last synced at: 14 days ago - Pushed at: 2 months ago - Stars: 1 - Forks: 1

samiyaalizaidi/Equalizer

Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications

Language: Verilog - Size: 536 KB - Last synced at: 4 days ago - Pushed at: 6 months ago - Stars: 7 - Forks: 1

ZipCPU/wb2axip

Bus bridges and other odds and ends

Language: Verilog - Size: 8.78 MB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 544 - Forks: 110

JeffDeCola/control-fpga-via-raspi-and-webserver

Control a FPGA via a Raspberry Pi and a Webserver.

Language: JavaScript - Size: 16.4 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 4 - Forks: 0

bsc-pm-ompss-at-fpga/ait

The Accelerator Integration Tool (AIT) automatically integrates OmpSs@FPGA accelerators into FPGA designs using different vendor backends

Language: Tcl - Size: 10.5 MB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 5 - Forks: 2

EMATech/zynq_book_pynq-z1

Zynq Book Tutorials adapted for the Digilent PYNQ-Z1

Language: Tcl - Size: 6.84 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

derekmulcahy/xvcpi

Xilinx Virtual Cable Server for Raspberry Pi

Language: C - Size: 290 KB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 113 - Forks: 28

klimatt/arty_a7

A playground with various modules, written in SystemVerilog, with a project setup to simplify working routines.

Language: SystemVerilog - Size: 27.7 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Wissance/QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Language: Verilog - Size: 127 KB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 22 - Forks: 7

continuum5531/RISC-V

This project features a 32-bit accumulator-based processor designed following the Von Neumann architecture, optimized for efficient computation. It implements a 16-opcode instruction set with multiple addressing modes, ensuring flexibility in instruction execution and data manipulation.

Language: Verilog - Size: 20.5 KB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

soham9284/Smart-Home-Automation-System

The Smart Home Automation System is a comprehensive solution that integrates sensors, manual controls, and automated logic to manage lighting, temperature, security, and emergency responses efficiently.

Language: Verilog - Size: 401 KB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

SUHANI102003/FSM-BASED-PROJECTS

Mini projects based on Finite State Machines (FSM)

Language: Verilog - Size: 735 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 1

Wissance/ImageCaptureSystem

A Xilinx IP Core and App for line scanner image capture and store

Language: VHDL - Size: 43.6 MB - Last synced at: 3 months ago - Pushed at: almost 8 years ago - Stars: 10 - Forks: 6

ADolbyB/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

Language: VHDL - Size: 5.58 MB - Last synced at: 4 months ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

gundasrikar/Sleepy-Keeper-FPGA-XILINX

Size: 1.95 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

soham9284/100_Days_of_Verilog

Language: Verilog - Size: 3.57 MB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

Anshuman-02/PWM-Generator-with-Variable-Duty-Cycle

VHDL project for a PWM Generator with variable duty cycle control and testbench simulation.

Language: VHDL - Size: 268 KB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

ultraembedded/usb2sniffer

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

Language: Verilog - Size: 1.2 MB - Last synced at: 4 months ago - Pushed at: about 5 years ago - Stars: 55 - Forks: 11

LijinWilson/traffic-light-controller

Traffic Light Controller This repository showcases the design and implementation of a Traffic Light Controller using Verilog. The project simulates a real-world traffic management system, ensuring smooth vehicle movement at intersections through an efficient state-based control mechanism.

Language: Verilog - Size: 35.2 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

10x-Engineers/Infinite-ISP_FPGABinaries

Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit and Efinix® Titanium Ti180 J484 Development Kit

Language: Python - Size: 52.4 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 6 - Forks: 4

Injabie3/dj-board

SFU - ENSC 452 (Advanced Digital System Design) Term Project: The Ultimate DJ Board using a Zedboard. Also mirrored on SFU CSIL's GitLab.

Language: VHDL - Size: 24.1 MB - Last synced at: 4 days ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 1

KareimGazer/PCI_Target_Device

Verilog simulation for a Target Device on a PCI bus with read and write transactions.

Language: Verilog - Size: 7.81 KB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 5

saikamat/AEP Fork of sappyh/AEP

Advanced Embedded Systems Project: Image Topology Extraction

Language: VHDL - Size: 76 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

bsc-pm-ompss-at-fpga/ompss-2-at-fpga-releases

Meta-repository for OmpSs-2@FPGA releases

Language: Makefile - Size: 67.4 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 1

henrikbrixandersen/elf-bootloader

SPI ELF bootloader for Xilinx Microblaze processors

Language: C - Size: 12.7 KB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 22 - Forks: 8

suoto/hdl_checker

Repurposing existing HDL tools to help writing better code

Language: Python - Size: 1.05 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 192 - Forks: 22

FrankKesel/xilinx_tools

Xilinx Tools Tutorials

Language: C++ - Size: 36.7 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

splAcharya/DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

Size: 71.2 MB - Last synced at: 8 months ago - Pushed at: almost 5 years ago - Stars: 18 - Forks: 4

caite21/CPU-Core

16-bit CPU Core Design in Verilog

Language: Tcl - Size: 283 KB - Last synced at: 4 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

deba0272/Verilog_SPI_Design

Size: 154 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

deba0272/NIELIT_VLSI_1_WEEK_TRAINING_PROGRAM

Size: 1.57 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

v-i-s-h-n-u-b/Traffic-light-controller

FPGA implementation of North South, East West, Emergency Vehicle Response, Pedestrian Crossing - Verilog

Size: 70.3 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

v-i-s-h-n-u-b/8-bit-CPU

Simple CPU Design in Verilog with MIPS-like Architecture, featuring Branch Prediction and Interrupt Control.

Size: 89.8 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

mongshil553/Digital-Engineering-Verilog-Assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

Language: Verilog - Size: 4.88 KB - Last synced at: 4 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

harshonyou/TSP-on-FPGA

FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.

Language: C - Size: 13.7 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 1

adamchristiansen/vivado-scripts 📦

Keep Xilinx Vivado projects as minimal git repositories. A fork of https://github.com/Digilent/digilent-vivado-scripts

Language: Tcl - Size: 29.3 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 1

Yellowflash-070/Oven-FSM-RTL-to-GDS-II-design-using-Qflow

RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.

Language: Verilog - Size: 22.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Yellowflash-070/32-bit-Signed-Vedic-Multiplier

A 32-bit Signed Vedic Multiplier created using Verilog HDL utilising Vedic Mathematic Sutras formed using Carry Lookahead Adders as the basic building blocks.

Language: Verilog - Size: 49.8 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

luminoso/cr-countones

Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs

Language: VHDL - Size: 25.6 MB - Last synced at: 8 months ago - Pushed at: almost 8 years ago - Stars: 7 - Forks: 1

riuandg5/eld-labs

Embedded Logic Design Labs

Language: Tcl - Size: 7.68 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

Prithvish04/reconfigurable_project

Canny edge detection in HLS

Language: Jupyter Notebook - Size: 10.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

Indithem/COL215-hardware-3

Filters and displays an image loaded into ROM through a VGA

Language: VHDL - Size: 63.3 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

matthiaskonrath/rc4-verilog

EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.

Language: C++ - Size: 169 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 7 - Forks: 0

conquerorcj26/i2C_Protocol_simulation

The objective of this project is to design and simulate i2C protocol using Verilog in Xilinx Vivado.

Language: Verilog - Size: 3.75 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1

Samuelbec025/Verilog-Matrix-Multiplier

This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.

Language: Verilog - Size: 75.2 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

BhattSoham/Euler-and-Modified-Euler-Hardware-Accelerator

Hardware Accelerator design for Euler and Modified method in solving ODE using VHDL language in Xilinx Vivado Environment

Language: VHDL - Size: 71.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

princeranjan03/ImageEncryption_I-CHIP

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

Language: Verilog - Size: 7.3 MB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

unipieslab/FREtZ

FPGA Reliability Evaluation through JTAG

Language: Tcl - Size: 31.6 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 7 - Forks: 0

sthanikan2000/Simple-Nano-Processor 📦

Simple Nano Processor | Group Project for CS1050-Computer Organization & Digital Design | Semester 02

Size: 12.9 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 2

NatsuDrag9/Kogge-Stone-Adder

Implementing a 4-bit Kogge Stone Adder (a type of carry-tree adder) in VHDL using XIlinx Vivado

Language: VHDL - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 2

z1skgr/reconf-Computing__HLS

High Level synthesis of data transfer in Vivado, Vivado HLS

Language: C++ - Size: 53.2 MB - Last synced at: 18 days ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

ArioKian/Xilinx_Zynq7000_PS_SLCR_RegistersDrivers

Zynq-7000 PS side drivers for SLCR Registers.

Language: C - Size: 6.84 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

BhattSoham/Implementation-of-Runge-Kutta-Hardware-Accelerator

Hardware Accelerator implementation for solving an ordinary differential equation using Runge Kutta Numerical methods using VHDL language

Language: VHDL - Size: 517 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

BhattSoham/Half-Precision-RK-Accelerator

Hardware Accelerator For Runge-Kutta solvers for ODE using Half Precision Floating Point Unit

Language: VHDL - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

BhattSoham/HW-Accelerator-for-Euler-Method-using-SP-FPunit

Implementation of a Hardware Accelerator for an ordinary differential equation using Euler method

Language: VHDL - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ArioKian/Xilinx_Zynq7000_ZynqUltraScalePlus_PS_SdCardDrivers

Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.

Language: C - Size: 7.81 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4x1MUX

The VHDL code implements a 4x1 multiplexer (MUX), selecting one of four input signals based on the two select lines and producing a single output.

Language: VHDL - Size: 42 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-DFlipFlop

The VHDL code describes a D flip-flop with synchronous reset functionality.

Language: VHDL - Size: 31.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-PriorityEncoder4x2

A 4x2 priority encoder is a digital circuit that takes four input lines and encodes them into a two-bit binary output based on the priority of the input lines.

Language: VHDL - Size: 68.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-Half_Adder

A half adder is a digital circuit that performs addition of two binary digits, generating the sum bit and the carry bit.

Language: VHDL - Size: 66.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-ShiftRegister

A VHDL shift register is a digital circuit implemented that allows sequential shifting of data bits either to the left or right within the register.

Language: VHDL - Size: 61.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-ArtyA7_Blinky

The code allows anyone with the Artix A7 FPGA Board to Blink the On-Board LED for any predefined Frequency.

Language: Tcl - Size: 32.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4Bit_UpDownCounter

A 4-bit up-down counter is a digital circuit capable of counting both upwards and downwards in binary, typically controlled by an up/down input signal.

Language: VHDL - Size: 41 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4Bit_UpCounter

A 4-bit up counter is a digital circuit that increments its output by one with each clock pulse, counting from 0000 to 1111 in binary, and resetting back to 0000 after reaching 1111.

Language: VHDL - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-2x4Decoder

The VHDL code implements a 2x4 decoder, converting two input signals into four output signals based on the input combinations.

Language: VHDL - Size: 40 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced at: about 1 year ago - Pushed at: about 7 years ago - Stars: 21 - Forks: 2

siorpaes/SimpleSoC

Very simple Cortex-M1 SoC design based on ARM DesignStart

Language: C - Size: 206 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 8 - Forks: 2

siorpaes/BareBonesCortexM0

Extremely basic CortexM0 SoC based on ARM DesignStart Eval

Language: Verilog - Size: 106 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 19 - Forks: 9

CLiz17/vending-machine

Verilog code for replicating a vending machine

Language: Verilog - Size: 2.93 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Luke7412/IpDemonstrators

Vivado demonstrator projects for IPs in IpLibrary repo.

Language: Python - Size: 257 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

gonzafernan/cese-mys-zynq7

Microarquitecturas y Softcores - CESE - FIUBA

Language: Verilog - Size: 1.25 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

Dhruv0Upadhyay/100_Days_of_RTL

100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog

Language: Verilog - Size: 1.05 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

Kampi/TinyAVR

VHDL design of an AVR8 CPU.

Language: VHDL - Size: 1.63 MB - Last synced at: 2 days ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 0

Multimedia-Processing/Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Language: Verilog - Size: 181 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 2

vinayak1998/Multiplier-Design

Language: VHDL - Size: 1.16 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

vinayak1998/Reflex-Tester

This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

Language: VHDL - Size: 1.02 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 4 - Forks: 0

vinayak1998/7-segment-display-fpga

Design and implement a Seven Segment Display available on the BASYS3 board (FPGA) in VHDL

Language: VHDL - Size: 455 KB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

nxbyte/Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Language: Verilog - Size: 2.23 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 91 - Forks: 21

hdlguy/make_for_vivado

experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.

Language: Tcl - Size: 1.04 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 21 - Forks: 0

simoneruffini/NORM

Framework for emulation of non volatile memory using off-the-shelf FPGAs

Language: VHDL - Size: 27.2 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 7 - Forks: 1

ChienKaiMa/2021_ACA_HLS_team05

High level synthesis projects and practices

Language: C++ - Size: 54.7 KB - Last synced at: 1 day ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

dwij2812/UART-Spectrum-Analyzer-for-Serial-Devices

The following Script can be used to generate certain mathematical functions on a micro controller or FPGA Device connected in serial based on the configuration selected by the the user and collect realtime data of the signal as generated by the device for spectrum analysis.

Language: VHDL - Size: 15 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 2 - Forks: 1