Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: multiplier

Repositories

contributte/forms-multiplier

:repeat: Form multiplier & replicator for Nette Framework

Language: PHP - Size: 225 KB - Last synced: 8 days ago - Pushed: 8 days ago - Stars: 26 - Forks: 20

pub-calculator-io/lcm-calculator

Free WordPress Plugin: LCM calculator to find the LCM of two or more numbers. Shows solutions by prime factorization, common multiples, cake/ladder, GCF, division, and Venn diagram. www.calculator.io/lcm-calculator/

Language: JavaScript - Size: 6.85 MB - Last synced: 10 days ago - Pushed: 11 days ago - Stars: 9 - Forks: 0

TheProlifical/msm

Welcome to the Maths Speed Multiplier website! Our aim is to provide a welcoming and respectful environment for all participants to practice math in a fun and supportive setting.

Language: CSS - Size: 2.84 MB - Last synced: 19 days ago - Pushed: 20 days ago - Stars: 1 - Forks: 0

GridSAT/CNF_FACT-MULT

CNF Generator for Factoring Problems

Language: Haskell - Size: 8.37 MB - Last synced: 26 days ago - Pushed: 2 months ago - Stars: 2 - Forks: 0

antonblanchard/vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Language: Python - Size: 3.02 MB - Last synced: about 1 month ago - Pushed: 8 months ago - Stars: 100 - Forks: 9

profitpulsecrypto65/ProfitPulse-Crypto-Multiplier-win32-x64

Your Trading Revolution ProfitPulse Crypto Multipliers reshapes the cryptocurrency trading landscape with its high-caliber predictive algorithms and seamless integration with top decentralized exchanges, PancakeSwap and Uniswap. It's engineered for both seasoned traders and newcomers, ensuring minimal risk and maximum profit.

Size: 16.6 KB - Last synced: about 1 month ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

JalalSayed1/N-bit-Multiplier

N-bit Multiplier implementation in VHDL

Language: VHDL - Size: 3.3 MB - Last synced: about 2 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

salzhang/Booth-Multiplier

Language: Verilog - Size: 55.7 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

rcetin/booth_wallace_multiplier

Booth encoded Wallace tree multiplier

Language: Verilog - Size: 8.79 KB - Last synced: about 2 months ago - Pushed: about 6 years ago - Stars: 14 - Forks: 4

splinedrive/kianRiscV

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .

Language: AGS Script - Size: 50.4 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 421 - Forks: 33

pmichaillat/stimulus-spending

Code and data for the paper "Optimal Public Expenditure with Inefficient Unemployment"

Language: MATLAB - Size: 18.6 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 0

akorkos/Digital-Electronic-Systems

Digital Circuits made with VHDL

Language: VHDL - Size: 2.98 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

ARohithReddy/multiplier

Digital circuit description to perform multiplication with data_path and control_path using verilog

Language: Verilog - Size: 155 KB - Last synced: 4 months ago - Pushed: almost 4 years ago - Stars: 0 - Forks: 1

CedricRev/simple-calculator-verilog

An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.

Language: Verilog - Size: 24.4 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

gubbriaco/FPGA-VHDL-Wallace-multiplier

Design and Analysis of an FPGA-based Wallace Multiplier.

Language: Jupyter Notebook - Size: 12.2 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

Saadia-Hassan/8x8Multiplier-Using-Vedic-Mathematics

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

Language: Verilog - Size: 4.88 KB - Last synced: 7 months ago - Pushed: almost 4 years ago - Stars: 5 - Forks: 2

vinayak1998/Multiplier-Design

Language: VHDL - Size: 1.16 MB - Last synced: 7 months ago - Pushed: over 6 years ago - Stars: 1 - Forks: 0

satishkumar1221/Project-Garuda-

Basic VHDL codes. Ask me for more codes and I will publish it in this repository.

Language: VHDL - Size: 41 KB - Last synced: 7 months ago - Pushed: about 7 years ago - Stars: 1 - Forks: 0

pmichaillat/countercyclical-multiplier

Code and data for the paper "A Theory of Countercyclical Government Multiplier"

Language: AMPL - Size: 66.4 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 2 - Forks: 0

paramrathour/Digital-Circuits-Lab

My VHDL Codes during EE214 (Digital Lab) Spring 2020-21

Language: VHDL - Size: 36.4 MB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

mmottaghi/bzfad

BZ-FAD: A low-power low-area multiplier based on shift-and-add architecture

Language: Verilog - Size: 699 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

Hassan313/Approximate-Multiplier

This repository contains approximate 8-bit multiplier Verilog code.

Language: Verilog - Size: 47 MB - Last synced: 22 days ago - Pushed: almost 4 years ago - Stars: 5 - Forks: 3

kamrul69/Multiplier-of-any-number

By using the code of python, you can make any multiplier of number. Enjoy!!

Language: Jupyter Notebook - Size: 3.91 KB - Last synced: 9 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

alighanbari2002/Booth-Multiplier Fork of M-Mashreghi/Booth-Multiplier

Verilog implementation of the Booth's multiplication algorithm.

Language: Verilog - Size: 689 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

saqibkh/Fast_Multipliers

Contains the RTL code and test benches for multipliers

Language: Verilog - Size: 68.8 MB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

suoglu/Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3

Language: Verilog - Size: 140 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 42 - Forks: 11

scale-lab/DRUM

The Verilog source code for DRUM approximate multiplier.

Language: Verilog - Size: 83 KB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 25 - Forks: 10

MrTejas/4-bit-multiplier

Design, Layout and performance analysis of a simple 4x4 multiplier circuit simulated in ngspice with power and time-delay calculations.

Language: Raku - Size: 505 KB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 0 - Forks: 0

nbathula16/SV-Project

32-bit Single Precision Floating point Multiplication

Language: SystemVerilog - Size: 5.99 MB - Last synced: 11 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

lorenzozaccomer/iterative-multiplier

Project for Electronic Calculators course.

Language: VHDL - Size: 4.77 MB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 0 - Forks: 0

greenelab/multi-plier

An unsupervised transfer learning approach for rare disease transcriptomics

Language: HTML - Size: 119 MB - Last synced: 9 months ago - Pushed: over 4 years ago - Stars: 41 - Forks: 11

suoglu/Carry-Save-Multiplier

Parameterized and 4-bit carry save multiplier design

Language: Verilog - Size: 48.8 KB - Last synced: 11 months ago - Pushed: about 3 years ago - Stars: 3 - Forks: 0

Centre-for-Hardware-Security/TTech-LIB

Language: Verilog - Size: 18.8 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 2 - Forks: 1

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Language: Verilog - Size: 1.51 MB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 62 - Forks: 26

Sanchit-20/Ten_Bit_Multiplier

Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.

Language: VHDL - Size: 777 KB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 2 - Forks: 0

RaulMurillo/Flo-Posit

Posit Arithmetic Cores generated with FloPoCo

Language: VHDL - Size: 447 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 11 - Forks: 6

tharunchitipolu/Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Language: Verilog - Size: 17.6 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 21 - Forks: 4

ZeroDashZero/32-bit-Multiplier-design-using-transistor-level-Digital-Gates

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

Size: 6.57 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 2 - Forks: 5