GitHub topics: processor-design

Repositories

Chufretalas/N_size_ALU

A very simple variable size ALU made in VHDL

Language: VHDL - Size: 14.6 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

luisalejandrobf/BoothsAlgorithm

Implementation of Booth's algorithm for signed binary multiplication. It includes code designed for the PDUA processor, developed by the Pontificia Universidad Javeriana. The algorithm is provided in assembly language and includes its translation into executable binary instructions.

Language: Assembly - Size: 71.3 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1 - Forks: 0

leticia-pontes/vhdl

Códigos e imagens de simulação de circuitos lógicos desenvolvidos em aula

Language: VHDL - Size: 544 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0

LasithaAmarasinghe/EN2031-Computer-Organization-and-Design

This includes assignments related to EN2031 - Computer Organization and Design semester 3 module at ENTC,UoM.

Size: 3.76 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

VadanShah/3-Stage-ALU-Pipeline-Processor

🚀 Verilog-based 3-stage pipelined ALU processor supporting ADD, SUB, AND, OR, MUL (Booth’s), and DIV (Restoring) operations.

Size: 0 Bytes - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

linukaratnayake/RV32I-Pipelined-Processor Fork of RISC-Processor/Pipelined-Processor

5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.

Language: Verilog - Size: 55.5 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

RISC-Processor/Pipelined-Processor

5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.

Language: Verilog - Size: 55.5 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 1

linukaratnayake/RV32I-Single-Cycle-Processor Fork of RISC-Processor/Single-Cycle-Processor

Single Cycle Non-Pipelined Processor for RV32I.

Language: Verilog - Size: 9.68 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

RISC-Processor/Single-Cycle-Processor

Single Cycle Non-Pipelined Processor for RV32I.

Language: Verilog - Size: 9.68 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 1

mpskex/chisel-npu

Chisel implementation of Neural Processing Unit for System on the Chip

Language: Scala - Size: 696 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 21 - Forks: 4

SKpro-glitch/RISCV-Processor-ASIC

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

Language: Verilog - Size: 138 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

shehanmunasinghe/tinyGPU

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

Language: SystemVerilog - Size: 1.23 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 45 - Forks: 9

aofarmakis/Nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

Language: Verilog - Size: 4.01 MB - Last synced at: 2 months ago - Pushed at: 7 months ago - Stars: 32 - Forks: 0

katef/eurorack-cpu

A CPU implemented in a modular synthesizer

Size: 33.7 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 303 - Forks: 8

astrogeekdk/RISC-V-Basic-SIMD

A basic implemention of 8 lane vector SIMD in RISC-V 5 Stage Pipeline, written in Chisel and Scala.

Language: Scala - Size: 12.7 KB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

darklife/udarkrisc

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

Language: Verilog - Size: 1.97 MB - Last synced at: 4 months ago - Pushed at: almost 2 years ago - Stars: 14 - Forks: 3

helcsnewsxd/famaf-computer_science-computer_architecture-lab1 📦

Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

Language: SystemVerilog - Size: 2.55 MB - Last synced at: 4 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

SarwanShah/HU_2021_RISC-V-Architecture-Verilog

In this project we implemented the RISC V processor architecture in Verilog.

Language: Verilog - Size: 12.7 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

tscheipel/HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Language: SystemVerilog - Size: 432 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 35 - Forks: 2

Assem-ElQersh/MIPS-Processor-Designs

Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.

Language: Verilog - Size: 13.7 KB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

Abd-El-Rahman-Sabry/rv32i-based-soc

A Verilog-based RISC-V processor featuring both single-cycle and pipelined implementations. The project supports a range of RISC-V instructions, including arithmetic, logical, load/store, and branching operations. Designed for educational and research purposes.

Language: Verilog - Size: 769 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Kokbddjkejsb/dOrv32

5-stage pipeline risc-v cpu

Size: 18.6 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

bansal-yash/COL216-Computer-Architecture

Course assignments of COL216:- Computer Architecture course at IIT Delhi under Professor Kolin Paul

Language: VHDL - Size: 37 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

Kevin-Caldwell/SimpleProcessor

Simple Single Bus RISCV Processor

Language: SystemVerilog - Size: 604 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

alirezakay/RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Language: VHDL - Size: 2.52 MB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 27 - Forks: 5

rj45/nanogo

NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs

Language: Go - Size: 1.26 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 2

mehmetakifkoz/MARS-Web-App

This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

Language: JavaScript - Size: 25.4 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

kara-abdelaziz/SEP-CPU

SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU

Language: Assembly - Size: 201 KB - Last synced at: 11 months ago - Pushed at: almost 4 years ago - Stars: 5 - Forks: 1

peilin-chen/Zhulong-RISCV-CPU

CPU Design Based on RISCV ISA

Language: Verilog - Size: 184 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 24 - Forks: 5

krishnakumardangi/pipe-MIPS32

It is a project on verilog which I had learned from a course taught by Prof. Indranil Sengupta at IIT Kharagpur.

Language: Verilog - Size: 74.2 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Benevanio/nodecsv

Projeto de leitura e processamento de dados de CSV em Node.js.

Language: JavaScript - Size: 14.6 KB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

AnkurRyder/8085-Processor

8-bit RISC Processor on Logisim

Size: 396 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 12 - Forks: 4

Amey-Thakur/COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

Language: C - Size: 152 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 14 - Forks: 2

lsjbh45/processor-design

Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)

Language: SystemVerilog - Size: 195 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

fatihkaan22/mips32-modified

Language: Verilog - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

ttqureshi/5-stage-pipelined-32-bit-Processor-RISC-V-ISA-

Implementing a 32-bit processor using RISC-V architecture.

Language: SystemVerilog - Size: 895 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ttqureshi/3-stage-pipelined-32-bit-Processor-RISC-V-ISA-

Implementation of 3 stage pipelined processor based on RISC-V Instruction Set Architecture

Language: SystemVerilog - Size: 1.95 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

JPedroSilveira/computer-organization-basics

Computer Organization (INF-UFRGS)

Size: 6 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

yth98/DSD_processor

A synthesizable pipelined RISC-V processor. (Digital System Design, Spring 2020, NTUEE)

Language: Verilog - Size: 22.6 MB - Last synced at: 12 months ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

jakujobi/BitBlaster_10bit_Processor

Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.

Language: SystemVerilog - Size: 181 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

DavidMorano/research

high instruction-level-parallelism (ILP) using Resource-Flow-Execution

Language: C - Size: 48.9 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

namiwijeuom/32-Bit-Non-Pipelined-Single-Cycle-Processor

This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

Language: SystemVerilog - Size: 35.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

hcshires/MIPS-Processors

CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations

Language: Python - Size: 22.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

Domain Specific Hardware Accelerators - VLSI CAD Project

Language: Bluespec - Size: 4.59 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2

JavidChaji/FUM-Computer-Architecture-Pipelined-MIPS-Processor

Pipelined MIPS Processor implementation, Computer Assignment for Computer Architecture course in Ferdowsi University of Mashhad

Language: Verilog - Size: 959 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

KonstantinosVasilopoulos/aueb_processor

A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.

Language: HTML - Size: 17.6 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

lazyoracle/vhdl-processor

An 8-bit processor in VHDL based on a simple instruction set

Language: VHDL - Size: 209 KB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 0

JavidChaji/FUM-Computer-Architecture-FUM-MIPS-Procssor-Design-Project-Desceription-TA

Language: TeX - Size: 2.32 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ajarlin/CS211-Computer-Architecture

Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.

Language: C - Size: 1.87 MB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

streetdogg/mips-cpu

Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design

Language: Verilog - Size: 98.6 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1

tugrul512bit/AdvancedMacroDevices

2D RPG/RTS/Simulation game that lets you design a CPU & manage your corporation against other corporations.

Language: C++ - Size: 8.48 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

vctrop/R8-core_FPGA_microcontroller

Microcontroller implementation (VHDL) using an expanded version of the R8 ISA (PUCRS), aiming FPGA synthesis

Language: Assembly - Size: 25.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Time0o/z80-verilog-report

Verilog Implementation of a Z80 Compatible Processor Architecture - Lab Report

Language: TeX - Size: 1.76 MB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

natruffles/FPG8

Verilog implementation of a computer architecture project (single-bus processor) on an iCEstick FPGA

Language: Verilog - Size: 803 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

kiriware/16-bit-RISC-Processor-Logisim

WIP Logic level implementation of a 16-bit processor in Logisim.

Size: 367 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

beyzanc/18-bit-processor-implementation-using-logisim

18-bit processor implementation using Logisim

Language: Python - Size: 530 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

daniel-santos-7/leaf

Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

Language: VHDL - Size: 660 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 3

JayKaku/RISC-V_MYTH_Workshop

RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Language: Python - Size: 5.5 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 1

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Language: Verilog - Size: 1.51 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 62 - Forks: 26

ChinmayMittal/COL216

Course repository for Computer Architecture, IIT Delhi 2021-22

Language: VHDL - Size: 5.57 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

lirui-shanghaitech/EE113_PROCESSOR

The reference design of EE113's final project (Digital integrated Circuit design Fall 2020) at ShanghaiTech University

Size: 742 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

Whitelisted2/CS311-CompArch-Lab

This repository contains files related to Computer Architecture Lab (Autumn 2022).

Language: Java - Size: 14.1 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

LeviBohnacker/EDRICO

EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and implement modern processor architectures.

Language: VHDL - Size: 23.7 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 2