Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: vlsi-cad

asyncvlsi/act

ACT hardware description language and core tools.

Language: C++ - Size: 4.81 MB - Last synced: about 22 hours ago - Pushed: 1 day ago - Stars: 93 - Forks: 22

PKU-IDEA/OpenPARF

🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit

Language: C++ - Size: 60 MB - Last synced: 1 day ago - Pushed: 1 day ago - Stars: 97 - Forks: 10

AUCOHL/Fault

A complete open-source design-for-testing (DFT) Solution

Language: Swift - Size: 4.21 MB - Last synced: about 1 month ago - Pushed: 2 months ago - Stars: 115 - Forks: 24

the-pinbo/EC704-VLSI-Design-Automation

EC704 - VLSI Design Automation

Language: Jupyter Notebook - Size: 14.2 MB - Last synced: about 2 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 1

the-pinbo/BooleanCalculator

boolean calculator engine using urp

Language: Python - Size: 80.1 KB - Last synced: about 2 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

neeraj1397/A-Primer-For-Physical-Design-Automation

This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.

Language: Jupyter Notebook - Size: 782 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 2 - Forks: 1

FarshidKeivanian/Minimization-of-Average-Power-Consumption-in-3-Stage-CMOS-Ring-Oscillator-based-on-MSFLA-Fuzzy-MSFL

FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)

Language: MATLAB - Size: 815 KB - Last synced: 4 months ago - Pushed: about 2 years ago - Stars: 1 - Forks: 2

Sudeep-Dhurua/verilog-to-gate-level-synthesis

This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.

Size: 0 Bytes - Last synced: 5 months ago - Pushed: about 3 years ago - Stars: 0 - Forks: 0

Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

Domain Specific Hardware Accelerators - VLSI CAD Project

Language: Bluespec - Size: 4.59 MB - Last synced: 3 months ago - Pushed: over 3 years ago - Stars: 6 - Forks: 2

the-pinbo/ROBDD

A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.

Language: Jupyter Notebook - Size: 5.39 MB - Last synced: about 2 months ago - Pushed: over 1 year ago - Stars: 2 - Forks: 1

paripath/cdf

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

Language: C++ - Size: 510 KB - Last synced: 10 months ago - Pushed: over 4 years ago - Stars: 12 - Forks: 4

CaiB/GDStoSVG

Converts GDSII (IC layout database) files to SVG (Vector graphics) files.

Language: C# - Size: 2.9 MB - Last synced: 10 months ago - Pushed: over 1 year ago - Stars: 6 - Forks: 6

rohankalbag/optiVLSI

A library for fast and optimized VLSI Computer-Aided-Design algorithms

Language: Python - Size: 90.9 MB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 1 - Forks: 1

karthik-r-rao/VLSI_Physical_Design_Tool

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

Language: Python - Size: 890 KB - Last synced: 7 months ago - Pushed: over 3 years ago - Stars: 5 - Forks: 3

ieee-ceda-datc/RDF-2019

DATC RDF

Language: Verilog - Size: 74.4 MB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 38 - Forks: 11

twweeb/VLSI-Physical-Design-Automation

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

Language: C++ - Size: 57.3 MB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 22 - Forks: 10

UdayaShankarS/TCL-Scripting

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

Language: Tcl - Size: 144 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 2 - Forks: 1

cuhk-eda/split-extract

Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation

Language: C++ - Size: 1020 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 2 - Forks: 2

rohankalbag/vlsi-circuit-partitioning-algorithms

Course Project - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: Jupyter Notebook - Size: 130 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0

HsuChiChen/vlsi

grayscale conversion system and simple convolution system

Language: Verilog - Size: 33.6 MB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 2 - Forks: 0

rohankalbag/logic-simulator

Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: Jupyter Notebook - Size: 95.7 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

Related Keywords
vlsi-cad 21 vlsi 9 vlsi-physical-design 6 vlsi-design 6 eda 5 design-automation 3 hspice 3 python 3 hardware-acceleration 2 algorithms 2 logic-simulator 2 python3 2 verilog-hdl 2 boolean-algebra 2 vlsi-circuits 2 cad 2 vlsi-floorplan 2 numba-jit 1 ram 1 vlsi-project 1 clock-tree 1 design-flow 1 ieee-ceda 1 ieee-ceda-datc 1 vector-processor 1 bdd 1 bdds 1 graphviz-dot 1 ipynb-jupyter-notebook 1 pthon3 1 robdd 1 characterization 1 power-analysis 1 spice-simulator 1 timing-analysis 1 converter 1 svg 1 automan 1 binary-decision-diagram 1 graph-algorithms 1 netlist 1 combinational-circuit 1 grayscale-image-converter 1 convolutional-neural-networks 1 networkx 1 kernighan-lin 1 graph-theory 1 eig-partitioning 1 clustering-algorithm 1 circuit-partitioning 1 manufacturing 1 intellectual-property 1 hardware-security 1 electronic-design-automation 1 deep-neural-networks 1 tcl-scripts 1 vlsi-routing 1 vlsi-placement 1 two-way-min-cut 1 physical-design-automation 1 nthu 1 global-routing 1 global-placement 1 fixed-outline 1 vlsi-design-flow 1 routing 1 placement 1 logic-synthesis 1 processor-design 1 urp 1 pcn 1 boolean-expression 1 graph 1 fiduccia-mattheyses 1 verilog 1 testing 1 stuck-at 1 scan-chains 1 jtag 1 fault-simulation 1 dft 1 atpg 1 fpga 1 prs 1 production-rules 1 language 1 hdl 1 hardware-description-language 1 dataflow-programming 1 dataflow 1 communicating-hardware-processes 1 circuit-simulator 1 chp 1 asynchronous-vlsi 1 asynchronous-circuits 1 processor-architecture 1 processor 1 hardware-designs 1 hardware 1 bus 1