GitHub topics: vlsi-cad
asyncvlsi/act
ACT hardware description language and core tools.
Language: C++ - Size: 4.89 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 108 - Forks: 27
CaiB/GDStoSVG
Converts GDSII (IC layout database) files to SVG (Vector graphics) files.
Language: C# - Size: 2.9 MB - Last synced at: 16 minutes ago - Pushed at: about 2 years ago - Stars: 12 - Forks: 4
himanshu5-prog/static_timing_analysis
This repo implements VLSI static timing analysis using C++.
Language: C++ - Size: 92.8 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
himanshu5-prog/vlsi_technology_mapping
This repository implements technology mapping using minimum cost tree-covering.
Language: C++ - Size: 433 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0
PKU-IDEA/OpenPARF
🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
Language: C++ - Size: 60 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 135 - Forks: 18
the-pinbo/ROBDD
A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.
Language: Jupyter Notebook - Size: 5.39 MB - Last synced at: 17 days ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1
AUCOHL/Fault
A complete open-source design-for-testing (DFT) Solution
Language: Swift - Size: 4.29 MB - Last synced at: 5 months ago - Pushed at: 6 months ago - Stars: 135 - Forks: 30
rohankalbag/optiVLSI
A library for fast and optimized VLSI Computer-Aided-Design algorithms
Language: Python - Size: 90.9 MB - Last synced at: 20 days ago - Pushed at: almost 2 years ago - Stars: 4 - Forks: 1
rohankalbag/logic-simulator
Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
Language: Jupyter Notebook - Size: 95.7 KB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
rohankalbag/vlsi-circuit-partitioning-algorithms
Course Project - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
Language: Jupyter Notebook - Size: 130 MB - Last synced at: 20 days ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 2
the-pinbo/EC704-VLSI-Design-Automation
EC704 - VLSI Design Automation
Language: Jupyter Notebook - Size: 14.2 MB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 1
neeraj1397/A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
Language: Jupyter Notebook - Size: 782 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 1
FarshidKeivanian/Minimization-of-Average-Power-Consumption-in-3-Stage-CMOS-Ring-Oscillator-based-on-MSFLA-Fuzzy-MSFL
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
Language: MATLAB - Size: 815 KB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 2
Sudeep-Dhurua/verilog-to-gate-level-synthesis
This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.
Size: 0 Bytes - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
Language: Bluespec - Size: 4.59 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2
paripath/cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
Language: C++ - Size: 510 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 12 - Forks: 4
karthik-r-rao/VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
Language: Python - Size: 890 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 3
ieee-ceda-datc/RDF-2019
DATC RDF
Language: Verilog - Size: 74.4 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 38 - Forks: 11
twweeb/VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
Language: C++ - Size: 57.3 MB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 22 - Forks: 10
UdayaShankarS/TCL-Scripting
Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference
Language: Tcl - Size: 144 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 1
cuhk-eda/split-extract
Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation
Language: C++ - Size: 1020 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 2
HsuChiChen/vlsi
grayscale conversion system and simple convolution system
Language: Verilog - Size: 33.6 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0
the-pinbo/BooleanCalculator
boolean calculator engine using urp
Language: Python - Size: 80.1 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0