GitHub topics: physical-design-automation
e3da/PowerSynth2-core
This is the PowerSynth backend with the command line interface (CLI)
Language: Python - Size: 8.17 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 4 - Forks: 3
EricLu1218/Physical_Design_Automation
2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design, Placement Legalization, Global Routing)
Language: Prolog - Size: 46.4 MB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 35 - Forks: 5
luk036/physdes-cpp
🧱 Physical design C++ Code
Language: C++ - Size: 673 KB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0
luk036/ckpttnpy
✂️ Circuit Partitioning Python Code
Language: Python - Size: 1.71 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
e3da/PowerSynth2-gui
This is the cross-platform PowerSynth 2 front end based on QT
Language: Python - Size: 248 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 2 - Forks: 1
MaoMao0414/NTHUCS_VLSIPDA_2023
Courseworks of VLSI Physical Design Automation, NTHU CS course teached by prof. Ting-Chi Wang in fall 2023
Language: Raku - Size: 15.9 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 0
therealczr15/NYCU_PDA_2024F
NYCU Physical Design Automation Fall 2024
Language: C++ - Size: 74.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0
azwad-tamir/gpt_gnn_3D_partitioner
A GPT-GNN based verilog netlist partitioner for 3D IC design
Language: Verilog - Size: 1.18 MB - Last synced at: 20 days ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 1
YubiYubi719/NYCU-Physical-Design-Automation
NYCU Physical Design Automation
Language: C++ - Size: 50.3 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
e3da/PowerSynth2-pkg
This contains the materials for the PowerSynth 2 release package excluding the source code
Language: MATLAB - Size: 51 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1 - Forks: 3
FelipeFFerreira/ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
Language: Verilog - Size: 186 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
e3da/PowerSynth1-src
PowerSynth 1 Series (v1.0-v1.9) Source Code
Language: Python - Size: 12.3 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
e3da/PowerSynth1-pkg
PowerSynth 1 Series (v1.0-v1.9) Package Materials
Language: MATLAB - Size: 127 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
twweeb/VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
Language: C++ - Size: 57.3 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 22 - Forks: 10
BWbwchen/FM-algorithm
The implementation of partition algorithm - Fiduccia and Mattheyses algorithm (FM algorithm) in C++
Language: C++ - Size: 18.1 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
Koyama-Tsubasa/VLSI_Physical_Design_Automation
Coursework of NTHU CS613500 VLSI Physical Design Automation
Language: C++ - Size: 17 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 0
