GitHub topics: physical-design
antonblanchard/vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
Language: Python - Size: 3.02 MB - Last synced at: 8 days ago - Pushed at: over 1 year ago - Stars: 112 - Forks: 9

ruisizhang123/PD_WM_GNN
[MLCAD'24] Automated Physical Design Watermarking Leveraging Graph Neural Networks & [TCAD'25] ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection
Language: C++ - Size: 87.8 MB - Last synced at: 21 days ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 1

eda-rs/netlist
generic NetList data structure for VLSI
Language: Verilog - Size: 17.8 MB - Last synced at: 22 days ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 2

DfX-NYUAD/Trojan-Insertion-versus-Layout-Defenses
Benchmarking framework for ISPD'23 contest and TCHES'25 paper.
Language: Shell - Size: 3.23 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 1

cda-tum/mnt-bench
MNT Bench - An MNT tool for Benchmarking FCN circuits
Language: HTML - Size: 1.56 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 11 - Forks: 0

cuhk-eda/cu-gr
CUGR, VLSI Global Routing Tool Developed by CUHK
Language: C++ - Size: 8.85 MB - Last synced at: 4 months ago - Pushed at: about 2 years ago - Stars: 125 - Forks: 40

cuhk-eda/Xplace
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
Language: C++ - Size: 81.3 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 102 - Forks: 9

cuhk-eda/ripple-fpga
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Language: C++ - Size: 5.46 MB - Last synced at: 5 months ago - Pushed at: about 5 years ago - Stars: 89 - Forks: 18

akilm/Physical-Design
Physical Design Flow from RTL to GDS using Opensource tools.
Size: 5.69 MB - Last synced at: 9 months ago - Pushed at: over 4 years ago - Stars: 72 - Forks: 13

Siddharth13s/RISC-V_Synthesis_and_Physical_Design
Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined repo
Language: Verilog - Size: 152 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

xkllkx/Physical_Design
N25K200 1121-NCKU-PHYSICAL DESIGN FOR NANOMETER IC'S Projects
Language: MATLAB - Size: 9.48 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

shobhit-mittra/vsd_pd_workshop
This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.
Size: 8.72 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

PokeyMystery/SerDes-Design-UVM-and-Physical-Design
SerDes RTL design, verification using UVM and Physical design.
Language: Verilog - Size: 1.21 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

shobhit-mittra/Tcl_parser
This repository is my entry into scripting using TCL and an attempt to understand it's nuances in physical design flow in VLSI
Language: Tcl - Size: 23.4 KB - Last synced at: 11 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

voidism/2019_CAD_Contest_ProblemE-testcase-visualizer
Testcase generator and visualizer and verification for your 2019 CAD Contest Problem E
Language: Python - Size: 12.7 KB - Last synced at: 12 months ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

eclufsc/ophidian
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Language: C++ - Size: 125 MB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 41 - Forks: 13

Pa1mantri/VSDMemSOC
VSDMemSOC Implementation flow:: RTL2GDSII
Language: Verilog - Size: 1.52 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

VardhanSuroshi/Vedic-Multiplier-From-RTL2GDS
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
Language: Verilog - Size: 6.6 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

shobhit-mittra/RTL-to-GDS2-flow
This repository is my attempt to get a hands-on-experience on the VLSI flow using Open-Source EDA tools.
Size: 939 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

gabrielganzer/DLX-Microprocessor
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
Language: Verilog - Size: 88.7 MB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 6 - Forks: 0

jordanpui/larf
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
Language: C++ - Size: 12.4 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 1

FelipeFFerreira/ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
Language: Verilog - Size: 186 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

cda-tum/sidb-defect-aware-physical-design
Design, layout, and simulation files of the paper "Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface" by M. Walter, J. Croshaw, S. S. H. Ng, K. Walus, R. Wolkow, and R. Wille in DATE 2024.
Language: C++ - Size: 25.1 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

scale-lab/OpenPhySyn
EDA physical synthesis optimization kit
Language: Verilog - Size: 134 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 46 - Forks: 9

gabrielganzer/VHDL-DesignSynthesis
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
Language: Verilog - Size: 7.4 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 0

puravbhatt/ASIC-Design-for-UART
Final project at San Jose State University
Size: 7.49 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

linkingmon/PD2020
Physical Design (2020 Spring)
Language: C++ - Size: 16.1 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0

ManjunathKalmath/CMOS_ASIC_Design-Lab
Contains the all the assignments of CMOS ASIC Design Lab
Size: 3.86 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1

wayne1204/Physical-Design
Physical Design for nanometer ICs @NTUEE
Language: C++ - Size: 23.1 MB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 1

Daikon-Sun/Physical-Design-for-Nanometer-ICs
Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
Language: C++ - Size: 37.4 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 27 - Forks: 15

BWbwchen/FM-algorithm
The implementation of partition algorithm - Fiduccia and Mattheyses algorithm (FM algorithm) in C++
Language: C++ - Size: 18.1 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

saathi7/Advanced-PD-using-OpenLANE-Sky130
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
Size: 3.71 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

Daikon-Sun/Routing-Visualization
Routing Visualization for Physical Design
Language: Python - Size: 1.11 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 12 - Forks: 4

Mrcuve0/MS-Labs
Source files for the labs of the Microelectronic Systems course
Language: VHDL - Size: 77.4 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 1
