brown9804/NexysDDR4-RISC-V_picorv32

Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU

Language: Verilog - Size: 85 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 3

pboechat/ice40up5k_riscv Fork of emeb/up5k_riscv

RISC-V SoC on the iCE40UP5K.

Language: C - Size: 540 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

efabless/caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Language: Verilog - Size: 14 GB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 319 - Forks: 82

efabless/caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Language: Verilog - Size: 3.61 GB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 135 - Forks: 136

filiparag/ftn-riscv-mcu 📦

Softcore microcontroller with peripherals based on PicoRV32

Language: Verilog - Size: 459 KB - Last synced at: 4 days ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

antonson-j1/SHA256-Accelerator-Hardware

This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog and synthesized using Yosys Open Synthesis Suite. The optimized designs are then compared with a base-line C implementation in software. Hash functions are used to securely store passwords, to quickly store and retrive data, and also to check if a file/message is corrupted.

Language: Verilog - Size: 3.66 MB - Last synced at: 7 months ago - Pushed at: over 3 years ago - Stars: 20 - Forks: 2

akilm/Physical-Design

Physical Design Flow from RTL to GDS using Opensource tools.

Size: 5.69 MB - Last synced at: 10 months ago - Pushed at: over 4 years ago - Stars: 72 - Forks: 13

JOKleinGe1/min_sys_riscv

Minimal system project with riscv core picorv32 : asm startup + linker script + c example + verilog system + testbench + Makefile

Language: Verilog - Size: 186 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 1

2uger/tiny_soc

Simple implementation of SOC around PicoRV32 soft core.

Language: Verilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

atx/gps-freq-counter

Frequency counter using a GPS receiver PPS output as its reference

Language: Scala - Size: 507 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 3

RISCV-MYTH-WORKSHOP/riscv-myth-workshop-sep23-fayizferosh

5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD

Language: Verilog - Size: 699 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

JunnanLi/picoSoC

SoC of PicoRV32i

Language: Verilog - Size: 558 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

wuhanstudio/picorv32_tang

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

Language: Python - Size: 543 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 18 - Forks: 3

wuhanstudio/picorv32_EG4S20

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

Language: Verilog - Size: 2 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 10 - Forks: 4

kanade-k-1228/mysoc

32bit RISC-V マイコン 🔥32bit RISC-V Microcontroller

Language: Verilog - Size: 364 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

michg/riscv32_beluga

c compiler beluga with riscv32 backend

Language: C - Size: 2.81 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 9 - Forks: 0

michg/riscv32_lcc

Language: C - Size: 3.23 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 11 - Forks: 4

MuratovAS/icesugar-riscv

A RiscV verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain

Language: Verilog - Size: 134 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

splinedrive/TangNano-9K-example Fork of sipeed/TangNano-9K-example

TangNano-9K-example project with kianRiscV cpu

Language: GLSL - Size: 1.34 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 2

tmahlburg/picosoc-basys3

Wrapper module for the PicoSoC to support the Digilent Basys 3

Language: Verilog - Size: 7.81 KB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

lnis-uofu/OpenFPGA-Softcores

Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

Language: Python - Size: 302 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

wuhanstudio/picorv32_MXO2

A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)

Language: Verilog - Size: 642 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 1

majorlin/xloader

Xilinx FPGA loader

Language: Verilog - Size: 330 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 1

Jesus89/picorv32-c-examples

C examples for picorv32 CPU

Language: C - Size: 672 KB - Last synced at: 3 months ago - Pushed at: over 9 years ago - Stars: 4 - Forks: 0

michg/cparserlibfirm_riscv32

Language: C - Size: 3.57 MB - Last synced at: almost 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0