stineje/sky130RHBDlib

Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130

Language: C - Size: 1.1 GB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 5 - Forks: 2

algofoogle/tt07-raybox-zero

TT07 resub of tt04-raybox-zero "3D" VGA ray caster demo (like Wolf3D)

Language: Verilog - Size: 1.71 MB - Last synced at: 15 days ago - Pushed at: 16 days ago - Stars: 2 - Forks: 0

google/skywater-pdk-sky130-raw-data

Raw data collected about the SKY130 process technology.

Language: Jupyter Notebook - Size: 15.6 MB - Last synced at: 23 days ago - Pushed at: about 2 years ago - Stars: 56 - Forks: 16

google/skywater-pdk-libs-sky130_fd_pr

Primitives for SKY130 provided by SkyWater.

Size: 109 MB - Last synced at: 23 days ago - Pushed at: about 1 year ago - Stars: 24 - Forks: 27

iic-jku/osic-multitool

JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

Language: Verilog - Size: 122 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 58 - Forks: 16

efabless/caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Language: Verilog - Size: 14 GB - Last synced at: about 1 month ago - Pushed at: 3 months ago - Stars: 319 - Forks: 82

google/skywater-pdk-libs-sky130_bag3_pr

BAG (BAG AMS Generator) Primitives Library for SKY130

Language: Python - Size: 3.26 MB - Last synced at: 23 days ago - Pushed at: almost 2 years ago - Stars: 18 - Forks: 6

iic-jku/SKY130_SAR-ADC1 Fork of w32agobot/SKY130_SAR-ADC

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

Language: Verilog - Size: 508 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 39 - Forks: 6

michaelk99/SKY130_CT-DSM

A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the front-end Gm-cell and a mixed-signal simulation w/ Ngspice.

Language: Jupyter Notebook - Size: 1.19 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 9 - Forks: 2

mattvenn/simulate-gate

Project 1.1 Simulate a Skywater 130nm standard cell using ngspice

Language: Makefile - Size: 68.4 KB - Last synced at: 7 days ago - Pushed at: about 1 year ago - Stars: 13 - Forks: 8

mattvenn/flipflop_demo

Flip flop setup, hold & metastability explorer tool

Language: Jupyter Notebook - Size: 34.1 MB - Last synced at: 7 days ago - Pushed at: over 2 years ago - Stars: 34 - Forks: 5

google/skywater-pdk-libs-sky130_fd_sc_hd 📦

"High density" digital standard cells for SKY130 provided by SkyWater.

Language: Verilog - Size: 207 MB - Last synced at: 23 days ago - Pushed at: about 2 years ago - Stars: 16 - Forks: 34

efabless/openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

Language: Python - Size: 31.4 MB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 272 - Forks: 54

JakobRat/RALF

Reinforcement learning assisted analog layout design flow.

Language: Python - Size: 421 MB - Last synced at: about 1 month ago - Pushed at: 11 months ago - Stars: 20 - Forks: 9

google/skywater-pdk-libs-sky130_fd_sc_lp 📦

"Low power" digital standard cells for SKY130 provided by SkyWater.

Language: Verilog - Size: 931 MB - Last synced at: 23 days ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 6

google/skywater-pdk-libs-sky130_fd_io

IO and periphery cells for SKY130 provided by SkyWater.

Language: Verilog - Size: 34 MB - Last synced at: 23 days ago - Pushed at: over 1 year ago - Stars: 10 - Forks: 11

kambadur/Projects

Everything related to MCUs, FPGAs, C, Verilog, Matlab/Simullink

Language: C - Size: 72.5 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

google/open-source-pdks

Index of the fully open source process design kits (PDKs) maintained by Google.

Size: 65.4 KB - Last synced at: 26 days ago - Pushed at: over 2 years ago - Stars: 92 - Forks: 8

Revenantx86/tiny-SAR

8-bit Succesive approximation register analog to digital converter (SAR-ADC)

Language: Makefile - Size: 328 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

google/skywater-pdk-libs-sky130_fd_bd_sram

SRAM build space for SKY130 provided by SkyWater.

Size: 1.09 MB - Last synced at: 23 days ago - Pushed at: over 3 years ago - Stars: 22 - Forks: 6

mattvenn/magic-mosfet

Project 1.2 Draw a MOSFET with Magic

Language: Makefile - Size: 19.5 KB - Last synced at: 7 days ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 6

efabless/caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Language: Verilog - Size: 3.61 GB - Last synced at: 5 months ago - Pushed at: about 3 years ago - Stars: 135 - Forks: 136

laurentc2/SKY130_for_KLayout

KLayout technology files for Skywater SKY130

Language: Makefile - Size: 24.4 MB - Last synced at: 5 months ago - Pushed at: almost 2 years ago - Stars: 38 - Forks: 12

google/skywater-pdk-libs-sky130_fd_sc_ms 📦

"Medium speed" digital standard cells for SKY130 provided by SkyWater.

Language: Verilog - Size: 920 MB - Last synced at: 23 days ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 5

google/skywater-pdk-libs-sky130_fd_sc_ls 📦

"Low speed" digital standard cells for SKY130 provided by SkyWater.

Language: Verilog - Size: 1.16 GB - Last synced at: 23 days ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 5

google/skywater-pdk-libs-sky130_fd_sc_hvl 📦

"High voltage" digital standard cells for SKY130 provided by SkyWater.

Language: Verilog - Size: 72 MB - Last synced at: 23 days ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 5

google/skywater-pdk-libs-sky130_fd_sc_hs 📦

"High speed" digital standard cells for SKY130 provided by SkyWater.

Language: Verilog - Size: 1.12 GB - Last synced at: 23 days ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 5

google/skywater-pdk-libs-sky130_fd_sc_hdll 📦

"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.

Language: Verilog - Size: 213 MB - Last synced at: 23 days ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 6

shalan/MS_QSPI_XIP_CACHE

AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP

Language: Verilog - Size: 525 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 6

algofoogle/tt08-vga-fun

Attempt at 24-bit (RGB888) VGA DAC

Language: Verilog - Size: 3.98 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 1

chennakeshavadasa/Low-dropout-Voltage-Regulator-LDO-using-SKY130PDK

Design of LDO using open source SKY130PDK

Size: 22.1 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 9 - Forks: 0

wulffern/rply_bias_sky130nm

PTAT bias current source for sky130nm

Language: HTML - Size: 625 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 1

mattvenn/instrumented_adder

Instrumenting adders to measure speed

Language: Verilog - Size: 13.1 MB - Last synced at: 7 days ago - Pushed at: almost 3 years ago - Stars: 13 - Forks: 3

Sajitha-Madugalle/cmos_inverter_sky130 Fork of SkillSurf/cmos_inverter_sky130

The repository contains an analysis and tapeout design process of a CMOS inverter under sky130 PDK. open source tools like Ngspice, Magic VLSI, Xschem has been used for design and simulations.

Size: 2.17 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

puxina/Open-VLSI

Repository for open-source tools to VLSI design

Language: Shell - Size: 30.3 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

arudeep15/NASSCOM-VSD-SOC

This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop.

Size: 33.8 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

ChrisZonghaoLi/sky130_ldo_rl

This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.

Language: Jupyter Notebook - Size: 5.16 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 21 - Forks: 3

fguzman82/upb_natalius_soc

8 bit RISC Processor for SKY 130nm process

Language: Verilog - Size: 56.3 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

litneet64/tt07-RO-based-PUF Fork of TinyTapeout/tt07-verilog-template

Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)

Language: Verilog - Size: 330 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

algofoogle/anton1-tt03 Fork of TinyTapeout/tt03-verilog-demo

Anton's "Simple Multiply" submission for Tiny Tapeout 3 (TT03)

Language: Verilog - Size: 64.5 KB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ACMmodel/MOSFET_model

A simple MOSFET model with only 5-DC-parameters for circuit simulation

Size: 7.76 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 29 - Forks: 5

pmicgen/pmicgen

Automated generation of a PMIC

Language: Jupyter Notebook - Size: 4.28 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 0

ShyamRazesh/DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING

2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)

Size: 249 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

w32agobot/SKY130_SAR-ADC

Fully-differential asynchronous non-binary 12-bit SAR-ADC

Language: Verilog - Size: 593 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 22 - Forks: 7

Tanmay707/NASSCOM-VSD-SOC

This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop

Size: 45.8 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Samrat-03/CMOS-Inverter

Study of characteristics of CMOS Inverter using open source EDA tools

Language: Tcl - Size: 1.07 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Pa1mantri/CellDesign

Adding a Customized Standard Cell into the OpenLane Flow

Size: 20.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

nelzeg/stdcell-library

A 12-track height standard cell library built in SKY130 PDK. The cells were designed using Magic VLSI Layout Tool and characterized using Digital Standard Cell Characterizer (DSCC).

Language: Python - Size: 9.44 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

nelzeg/stdcell-characterizer

Python-based electronic design automation (EDA) tool for characterizing digital standard cells designed in SKY130 PDK. The characterization process is based in the Synopsys Liberty User Guides and Reference Manual Suite - Version 2017.06

Language: Python - Size: 9.68 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

manili/LDF

Layout Description Framework, a framework to help semi-custom or full-custom designers create the layout of their ICs by writing C# code.

Language: C# - Size: 266 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

mattvenn/wrapped_project_template

Template project for the Zero to ASIC course group ASIC application

Language: Verilog - Size: 85.4 MB - Last synced at: 7 days ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 10

mattvenn/zero_to_asic_mpw6

MPW6 submission from the Zero to ASIC Course

Language: Verilog - Size: 170 MB - Last synced at: 7 days ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 1

ShonTaware/LowPower

Various low power labs using sky130

Language: Verilog - Size: 5.8 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 6 - Forks: 5

ridvanumaz/2AC_Folded-Cascode-OTA-with-SKY130-PDK

A folded-cascode OTA with 3.3V power supply and 54.27 dB DC gain with 66.8MHz unity frequency

Size: 1.07 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

ridvanumaz/1AC_Beta-multiplier-and-bias-circuit-with-SKY130-PDK

Generating 40μA bias current with a supply voltage of 3.3V using SKY130 PDK

Size: 1.05 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

aasthadave9/Advanced-Physical-Design-Using-OpenLANE-Sky130

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

Size: 467 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 7 - Forks: 6

ShonTaware/OpenSource_Physical_Design

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

Size: 4.96 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 15

AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

Size: 1.3 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 8 - Forks: 4

PSR0001/eSim_hackathon

Mixed Signal Circuit Design and Simulation Marathon under very Good category Article: https://www.linkedin.com/pulse/mixed-signal-simulation-marathon-using-esim-sky130-kannan-moudgalya/?trackingId=PLrgw35VThqQ5QB

Language: Verilog - Size: 3.96 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

arpit306/VSD-IAT-Sign-off-Timing-Analysis-Basics-to-Advanced

In this workshop we studied the concepts involved in STA from basics to advanced, with the help of open source STA tools and libraries.

Size: 54.7 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

saathi7/Advanced-PD-using-OpenLANE-Sky130

Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD

Size: 3.71 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

ShonTaware/SRAM_SKY130

Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

Language: SourcePawn - Size: 20.2 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 23 - Forks: 7

malivinayak/Self-Correcting-Message-System-using-Hamming-Code

Self-Correcting Message System using Hamming Code

Language: Verilog - Size: 6.14 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

eescottie/opensrc_tools_pdk

Record down how to install the open-source tools and PDK on Ubuntu OS for analog IC design

Size: 33.2 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

junior-jl/cs-amp-sky130

Design of a common source amplifier using Skywater sky130 technology

Size: 3.08 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

kambadur/sky130RTLDesignAndSynthesisWorkshop

This is a 5-day workshop on RTL Design and Synthesis using open source tools for logic design, simulation, synthesis and technology mapping with Sky130 PDK. (iVerilog, GTKwave, Yosys and Sky130 technology)

Size: 4.33 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1

TobiasKaiser/sky130-3d-render

Language: Shell - Size: 139 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

rsmarinho/circuit-samples

Circuit samples and simulations for sky130 pdk and other generalities.

Size: 53.7 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0