GitHub topics: caravel
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language: Python - Size: 836 MB - Last synced at: 12 days ago - Pushed at: 3 months ago - Stars: 1,487 - Forks: 395
efabless/caravel
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
Language: Verilog - Size: 14 GB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 319 - Forks: 82
FPGA-Research/FABulous_board
A PCB created for FABulous FPGAs, based on the caravel board.
Language: Python - Size: 11 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 1
efabless/caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Language: Verilog - Size: 3.61 GB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 135 - Forks: 136
0x01be/rudder
Learn, share and collaborate on ASIC design using open tools and technologies
Language: Dockerfile - Size: 6.01 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 10 - Forks: 1
efabless/clear_old
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
Language: Verilog - Size: 265 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0
neevany/caravel-on-heroku 📦
One-button Heroku deploy for the Caravel data exploration platform.
Language: Python - Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: over 8 years ago - Stars: 9 - Forks: 65
efabless/caravel_ibex
An example project that utilizes caravel user space for an ibex based SoC
Language: Verilog - Size: 567 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 4
kbeckmann/caravel-pll-calculator
PLL configuration generator for the Caravel management core
Language: Python - Size: 12.7 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 10 - Forks: 0
erikvanzijst/wrapped_pong
An ASIC running Pong.
Language: Verilog - Size: 19.5 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1
