stnolting/neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Language: VHDL - Size: 846 KB - Last synced at: about 2 hours ago - Pushed at: about 3 hours ago - Stars: 75 - Forks: 24

nturley/netlistsvg

draws an SVG schematic from a JSON netlist

Language: JavaScript - Size: 1.02 MB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 692 - Forks: 89

DuttPanchal04/rtl-design-and-synthesis-using-icarus-verilog-gtkwave-yosys

A collection of Verilog-based RTL design projects with testbenches, simulated using Icarus Verilog and GTKWave. This repo showcases foundational digital logic circuits as part of my VLSI learning journey using open-source tools.

Language: Verilog - Size: 6.52 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

YoWASP/yosys

Unofficial Yosys WebAssembly packages

Language: Python - Size: 269 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 70 - Forks: 2

freand76/digsim

An interactive digital logic simulator with verilog support (Yosys)

Language: Python - Size: 1.45 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 19 - Forks: 0

johnnycubides/digital-electronic-1-101

Language: Verilog - Size: 39.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 6 - Forks: 2

imagarchive/rlst

A Redstone Logic Synthesis Tool because Redstone written in VHDL is cool (IN DEVELOPMENT)

Language: C++ - Size: 200 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language: Python - Size: 836 MB - Last synced at: 5 days ago - Pushed at: 2 months ago - Stars: 1,476 - Forks: 394

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.09 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 682 - Forks: 200

CSharperMantle/ysyx-chip-area-visualizer

Y Chip Area Visualizer: Visualize Yosys `stat` reports.

Language: TypeScript - Size: 1.57 MB - Last synced at: 5 days ago - Pushed at: 10 days ago - Stars: 5 - Forks: 0

aGhandhii/icebreaker-fpga-systemverilog-dev-environment

Open-Source SystemVerilog Development Environment for 1BitSquared FPGA Development Boards

Language: Shell - Size: 9.77 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

m-labs/nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

Language: Python - Size: 1.3 MB - Last synced at: 4 days ago - Pushed at: over 3 years ago - Stars: 669 - Forks: 59

mattvenn/fpga-sdft

sliding DFT for FPGA, targetting Lattice ICE40 1k

Language: Verilog - Size: 183 KB - Last synced at: 5 days ago - Pushed at: about 5 years ago - Stars: 76 - Forks: 16

Pa1mantri/TCL_Scripting

TCL Script to automate the generation of Pre-layout QoR results

Language: Verilog - Size: 6.38 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 0 - Forks: 0

apfaudio/eurorack-pmod

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

Language: SystemVerilog - Size: 27.7 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 203 - Forks: 13

PyFPGA/pyfpga

A Python package to use FPGA development tools programmatically.

Language: Python - Size: 7.15 MB - Last synced at: 15 days ago - Pushed at: about 2 months ago - Stars: 130 - Forks: 15

zachjs/sv2v

SystemVerilog to Verilog conversion

Language: Haskell - Size: 2.19 MB - Last synced at: 19 days ago - Pushed at: about 1 month ago - Stars: 616 - Forks: 58

divadnauj-GB/stereo_vision_core

Stereo Vision Core accelerator is a real-time stream processing architecture that calculates the disparity map of stereo images. The accelerator is available as an RTL description using VHDL, which is fully parametrizable and synthetizable for FPGA or ASIC.

Language: VHDL - Size: 66 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 4 - Forks: 0

multigcs/LinuxCNC-RIO

RealtimeIO for LinuxCNC based on an FPGA

Language: Python - Size: 28 MB - Last synced at: 4 days ago - Pushed at: 8 months ago - Stars: 77 - Forks: 17

ElecGeek/PulsesGene

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

Language: VHDL - Size: 180 KB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 0 - Forks: 0

cariboulabs/cariboulite

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

Language: C - Size: 234 MB - Last synced at: 28 days ago - Pushed at: 3 months ago - Stars: 1,190 - Forks: 118

Pratim-Senapati/qflow-projects

A complete setup for Qflow, an open-source digital VLSI design flow. This repo provides pre-configured example projects, automated installation scripts, and step-by-step instructions to synthesize, place, and route Verilog designs into GDSII layouts. Supports both running example designs and using your own Verilog.

Language: Python - Size: 7.85 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

YoWASP/boolector

Unofficial nextpnr WebAssembly packages

Language: Shell - Size: 38.1 KB - Last synced at: 21 days ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 1

shrine-maiden-heavy-industries/torii-hdl

A modern hardware definition language and toolchain based on Python

Language: Python - Size: 1.16 GB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 16 - Forks: 1

Lukas0025/yosys-cgploss

use genetic algoritms for optimalize circuits

Language: C++ - Size: 426 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

nishit0072e/RTL-to-GDSII

Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation

Language: C++ - Size: 7.85 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 7 - Forks: 0

charlottia/hdx 📦

HDL development environment on Nix.

Language: Python - Size: 169 KB - Last synced at: 4 days ago - Pushed at: 7 months ago - Stars: 25 - Forks: 0

nishit0072e/openlane-flow

Openlane is a complete RTL-to-GDS flow, which uses openroad for floorplan, placement etc.

Language: Jupyter Notebook - Size: 2.89 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

romavis/lwdo-sdr-fw

LWDO-SDR firmware (FPGA & FTDI)

Language: Verilog - Size: 353 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 8 - Forks: 2

BDSM-hardware/lock_handler

Manages multi points bondage locks, for self or collective bondage.

Language: PostScript - Size: 2.85 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 3 - Forks: 0

efabless/caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Language: Verilog - Size: 14 GB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 319 - Forks: 82

chipsalliance/yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Language: Verilog - Size: 4.57 MB - Last synced at: about 1 month ago - Pushed at: 12 months ago - Stars: 83 - Forks: 47

sifferman/fusesoc_template

Example of how to get started with olofk/fusesoc.

Language: Python - Size: 10.7 KB - Last synced at: 5 days ago - Pushed at: almost 4 years ago - Stars: 17 - Forks: 0

SymbiFlow/sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

Language: Python - Size: 153 KB - Last synced at: about 11 hours ago - Pushed at: over 1 year ago - Stars: 59 - Forks: 16

nishtahir/icicle

An OSS CAD Suite Version Manager

Language: Rust - Size: 107 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 0

tmeissner/psl_with_ghdl

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

Language: VHDL - Size: 92.8 KB - Last synced at: 6 days ago - Pushed at: 3 months ago - Stars: 66 - Forks: 5

JochiSt/TangPrimer20K_DockExt

OpenSource tool usage for TangPrimer 20K with the DockExt Board

Language: Makefile - Size: 18.6 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

chili-chips-ba/openXC7-TetriSaraj

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

Language: Verilog - Size: 25.1 MB - Last synced at: about 1 month ago - Pushed at: 3 months ago - Stars: 24 - Forks: 1

mmicko/enigmaFPGA

Enigma in FPGA

Language: Verilog - Size: 1.92 MB - Last synced at: 19 days ago - Pushed at: almost 6 years ago - Stars: 29 - Forks: 3

PyFPGA/HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Language: Python - Size: 5.15 MB - Last synced at: 6 days ago - Pushed at: 2 months ago - Stars: 24 - Forks: 2

Kenny2github/V2MC

Synthesize Verilog to Minecraft redstone

Language: Python - Size: 194 KB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 14 - Forks: 1

AbinashDwibedi/learning-verilog

A repository dedicated to learning Verilog, featuring examples, testbenches, simulations, and gate-level designs. Perfect for beginners and enthusiasts exploring hardware description languages.

Language: Verilog - Size: 1.35 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

tvlad1234/violet

Virtual I/O for FPGAs

Language: Verilog - Size: 58.6 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

YosysHQ/padring

A padring generator for ASICs

Language: C++ - Size: 177 KB - Last synced at: about 1 month ago - Pushed at: almost 2 years ago - Stars: 25 - Forks: 9

kambadur/Projects

Everything related to MCUs, FPGAs, C, Verilog, Matlab/Simullink

Language: C - Size: 72.5 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

kittennbfive/5A-75B-tools

a collection of tools made while messing with the Colorlight 5A-75B V7.0 and some notes using ECP5 with Yosys

Language: HTML - Size: 3.38 MB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 19 - Forks: 3

Werni2A/Valhalla-II

Open-Source VHDL Synthesis for Alhambra II FPGA Board

Language: VHDL - Size: 22.5 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 2

ghdl/docker

Scripts to build and use docker images including GHDL

Language: Shell - Size: 250 KB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 42 - Forks: 11

osresearch/risc8

Mostly AVR compatible FPGA soft-core

Language: Verilog - Size: 278 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 27 - Forks: 3

PyFPGA/containers

Containers for FOSS tools

Language: Shell - Size: 31.3 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

sifferman/fusesoc_project_template

A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

Language: Makefile - Size: 4.88 KB - Last synced at: 5 days ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

kivikakk/zxxrtl

Idiomatic CXXRTL bindings for Zig

Language: Zig - Size: 9.77 KB - Last synced at: 15 days ago - Pushed at: 7 months ago - Stars: 4 - Forks: 1

ben-marshall/croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

Language: SystemVerilog - Size: 754 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 44 - Forks: 7

tmeissner/gatemate_experiments

Experiments with Cologne Chip's GateMate FPGA architecture

Language: VHDL - Size: 114 KB - Last synced at: 6 days ago - Pushed at: over 1 year ago - Stars: 15 - Forks: 1

racerxdl/tangnano-yosys-hello

Sipeed Tang Nano Fully Opensource Toolchain Ledblink

Language: Makefile - Size: 4.88 KB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 32 - Forks: 5

JochiSt/icebreaker-VHDL

Some examples using VHDL in combination with the icebreaker board

Language: Makefile - Size: 14.6 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

standardsemiconductor/yosys-rtl

Yosys RTL ▷ Haskell

Language: Haskell - Size: 26.4 KB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

tmeissner/formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

Language: VHDL - Size: 205 KB - Last synced at: 6 days ago - Pushed at: about 1 year ago - Stars: 41 - Forks: 7

efabless/caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Language: Verilog - Size: 3.61 GB - Last synced at: 5 months ago - Pushed at: about 3 years ago - Stars: 135 - Forks: 136

brown9804/VerilogCircuitDesignsHub

Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.

Language: Verilog - Size: 4.76 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 0

chipsalliance/fpga-tool-perf

FPGA tool performance profiling

Language: Python - Size: 9.69 MB - Last synced at: 1 day ago - Pushed at: about 1 year ago - Stars: 102 - Forks: 29

DoctorWkt/ULX3S-Blinky

A blinky project for the ULX3S v3.0.3 FPGA board

Language: Verilog - Size: 588 KB - Last synced at: 3 months ago - Pushed at: about 6 years ago - Stars: 16 - Forks: 6

pat-pgt/MultiFrequenciesDetector

Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.

Language: VHDL - Size: 271 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

mcejp/Poly94

Yet another faux-retro game system

Language: Verilog - Size: 1.48 MB - Last synced at: 1 day ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 0

akilm/Physical-Design

Physical Design Flow from RTL to GDS using Opensource tools.

Size: 5.69 MB - Last synced at: 9 months ago - Pushed at: over 4 years ago - Stars: 72 - Forks: 13

alangarf/tm1638-verilog

A basic verilog driver for the TM1638 LED and key matrix chip

Language: Verilog - Size: 1.31 MB - Last synced at: about 1 month ago - Pushed at: over 7 years ago - Stars: 17 - Forks: 2

Alfredosavi/tangnano-hello

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

Language: Makefile - Size: 8.79 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 1

douwedevries/tangnano20k

Basic counter example in verilog for Tang Nano 20k using Yosys, Nextpnr and openFPGALoader.

Language: Verilog - Size: 12.7 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

multigcs/FPGA-blinky

Language: Makefile - Size: 92.8 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 3 - Forks: 1

nathsou/hdl-env

Dev container for development and simulation of the Nandland Go and Alchitry Cu FPGA Boards using open source software.

Language: Verilog - Size: 22.5 KB - Last synced at: 2 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

porglezomp/nangate

Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)

Language: C++ - Size: 2.93 KB - Last synced at: about 1 month ago - Pushed at: about 6 years ago - Stars: 7 - Forks: 0

embed-dsp/ed_yosys

Compile and install of Yosys. Yosys is a framework for Verilog RTL synthesis.

Language: Makefile - Size: 2.93 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

maazm007/vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Language: C - Size: 5.79 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 5 - Forks: 0

BhattSoham/RISCV-HDP

Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)

Language: Verilog - Size: 42.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Pa1mantri/VSD_Hardware_Design

Pre and Post Synthesis Simulation of a Design VSDMemSOC

Language: Verilog - Size: 6.49 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

lushaylabs/tangnano9k-series-examples

Examples for the Lushay Labs tang nano 9k series

Language: GLSL - Size: 789 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 63 - Forks: 13

atoomnetmarc/FPGA-playground

Random collection of FPGA related stuff.

Language: Verilog - Size: 3.05 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

dpretet/meduram

Multi-port BRAM IP for ASIC and FPGA

Language: SystemVerilog - Size: 241 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 10 - Forks: 2

Pa1mantri/VSDMemSOC

VSDMemSOC Implementation flow:: RTL2GDSII

Language: Verilog - Size: 1.52 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Essenceia/MoldUPD64

RTL implementation of a MoldUPD64 receiver.

Language: Verilog - Size: 2.68 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

sjkeller/smart-sensors-project

Verilog implementations of different simple tasks

Language: Verilog - Size: 411 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

augustofg/ice40-ghdl

VHDL examples targeting the ICE40-HX8K development board using iceStorm + GHDL

Language: VHDL - Size: 27.3 KB - Last synced at: 5 days ago - Pushed at: almost 2 years ago - Stars: 4 - Forks: 1

Tech-mohankrishna/pes_bcdbin

This repository deals with BCD to binary conversion using iverilog as a simulator and yosys as a synthesis tool.

Language: Verilog - Size: 64.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

sachinkum0009/goertzel-filter-vhdl

Design a Goertzel filter

Language: VHDL - Size: 86.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

streetdogg/hardware-designs

Verilog Implementation for various Hardware on Lattice FPGA using the Open-source Yosys toolchain.

Language: Verilog - Size: 25.4 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

fayizferosh/yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

Language: Verilog - Size: 1.17 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 0

rohanverma94/200DaysWithFPGAs

The objective of this project is to explore ray tracing and design a soft GPU on Xilinx Artix 100T.

Size: 3.91 KB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

franzflasch/leiwand_rv32

RISC-V RV32I CPU written in verilog

Language: Verilog - Size: 395 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 0

vanbwodonk/oss-cad-suite-build-bin

Nightly Arch Linux Package oss-cad-suite-build-bin

Language: Shell - Size: 102 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

kokjo/misc_fpga

iCE40 and ECP5 fpga libraries and projects. Using the open source toolchain yosys+nextpnr. Quality may vary.

Language: Verilog - Size: 41 KB - Last synced at: almost 2 years ago - Pushed at: almost 6 years ago - Stars: 4 - Forks: 1

XarkLabs/upduino-example

Example UPduino project setup for Linux, macOS and WIndows+WSL for synthesis and simulation

Language: Makefile - Size: 120 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 6 - Forks: 1

varkenvarken/robin

SoC design targeted at the IceBreaker board

Language: Assembly - Size: 7.32 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 5 - Forks: 0

abdelazeem201/OpenLane Fork of The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Size: 833 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

vmunoz82/eda_tools

A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.

Language: Dockerfile - Size: 17.6 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 24 - Forks: 4

ECP5-PCIe/ECP5-PCIe

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

Language: Python - Size: 43 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 83 - Forks: 5

lethalbit/yosys-vscode

Syntax Highlighting for Yosys Scripts and RTLIL

Size: 341 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 5 - Forks: 0

embedded-explorer/Open-Source-RTL-Design

This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop

Language: Verilog - Size: 10.8 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 15 - Forks: 5

cjacker/opensource-embeded-toolchains

Embeded Toolchains in opensource way

Size: 95.7 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 4 - Forks: 1

MuratovAS/micro-yosyslint 📦

Verilog linting plugin for Micro editor. Checks the syntax of the Language Verilog. Based on yosys.

Language: Lua - Size: 252 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

PyFPGA/openflow

A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.

Language: Python - Size: 24.4 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 1