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GitHub / aGhandhii / icebreaker-fpga-systemverilog-dev-environment

Open-Source SystemVerilog Development Environment for 1BitSquared FPGA Development Boards

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aGhandhii%2Ficebreaker-fpga-systemverilog-dev-environment

Stars: 0
Forks: 0
Open issues: 0

License: None
Language: Shell
Size: 9.77 KB
Dependencies parsed at: Pending

Created at: 5 months ago
Updated at: about 1 month ago
Pushed at: about 1 month ago
Last synced at: about 1 month ago

Topics: foss, lattice-ice40, systemverilog, yosys

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