GitHub topics: yosys-plugin
chipsalliance/yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
Language: Verilog - Size: 4.57 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 83 - Forks: 47
porglezomp/nangate
Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)
Language: C++ - Size: 2.93 KB - Last synced at: 3 months ago - Pushed at: about 6 years ago - Stars: 7 - Forks: 0
albmoriconi/yosys-als
A design space exploration tool for approximate circuits
Language: C++ - Size: 264 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 1
lethalbit/discretize
A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad
Language: C++ - Size: 2.88 MB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 11 - Forks: 0
MuratovAS/micro-yosyslint 📦
Verilog linting plugin for Micro editor. Checks the syntax of the Language Verilog. Based on yosys.
Language: Lua - Size: 252 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
