Ecosyste.ms: Repos
An open API service providing repository metadata for many open source software ecosystems.
GitHub topics: logic-synthesis
workcraft/workcraft
Toolset to capture, simulate, synthesize and verify graph models
Language: Java - Size: 63.6 MB - Last synced: about 14 hours ago - Pushed: about 17 hours ago - Stars: 55 - Forks: 142
hriener/easy
C++ header-only ESOP library
Language: C++ - Size: 1.87 MB - Last synced: 2 days ago - Pushed: 3 days ago - Stars: 8 - Forks: 4
NYU-MLDA/ALMOST
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning
Language: Verilog - Size: 74.1 MB - Last synced: 7 days ago - Pushed: 7 days ago - Stars: 2 - Forks: 0
NYU-MLDA/ABC-RL
This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
Language: Verilog - Size: 21.1 MB - Last synced: 11 days ago - Pushed: 11 days ago - Stars: 1 - Forks: 0
The-OpenROAD-Project/yosys Fork of YosysHQ/yosys
Logic synthesis and ABC based optimization
Language: C++ - Size: 24.5 MB - Last synced: 12 days ago - Pushed: 12 days ago - Stars: 40 - Forks: 40
panhomyoung/phyLS
A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""
Language: C++ - Size: 10.3 MB - Last synced: 10 days ago - Pushed: 11 days ago - Stars: 13 - Forks: 2
lnis-uofu/LSOracle
IDEA project source files
Language: Verilog - Size: 547 MB - Last synced: 1 day ago - Pushed: over 1 year ago - Stars: 87 - Forks: 41
snowkylin/npn
A boolean matcher that computes the NPN canonical representative for a given boolean function.
Language: C++ - Size: 20.5 KB - Last synced: 27 days ago - Pushed: about 2 months ago - Stars: 0 - Forks: 1
cda-tum/fiction
An open-source design automation framework for Field-coupled Nanotechnologies
Language: C++ - Size: 19.1 MB - Last synced: 29 days ago - Pushed: 29 days ago - Stars: 51 - Forks: 21
changmg/ResubALS
Efficient resubstitution-based approximate logic synthesis
Language: C++ - Size: 4.16 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 2 - Forks: 0
cornell-zhang/HOGA
Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
Language: Python - Size: 488 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 17 - Forks: 0
lsils/lstools-showcase
Showcase examples for EPFL logic synthesis libraries
Language: CSS - Size: 21.2 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 155 - Forks: 30
clin99/awesome-eda
Size: 51.8 KB - Last synced: about 1 month ago - Pushed: almost 5 years ago - Stars: 84 - Forks: 19
msoeken/kitty
C++ truth table library
Language: C++ - Size: 818 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 40 - Forks: 75
animeshbchowdhury/RTL_dataset
Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys
Language: Verilog - Size: 6.92 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0
msoeken/cirkit
A circuit toolkit
Language: C++ - Size: 15.8 MB - Last synced: 22 days ago - Pushed: about 4 years ago - Stars: 90 - Forks: 37
NTU-ALComLab/IWLS2021 📦
Code repository for the IWLS 2021 Programming Contest
Language: Python - Size: 602 MB - Last synced: 4 months ago - Pushed: 10 months ago - Stars: 1 - Forks: 1
BUPTslb/LIMGEN
This project will be the beginning of my research life!
Language: C++ - Size: 29.1 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0
Po-Chun-Chien/FringeDT 📦
An implementation of binary decision tree with fringe-features extraction.
Language: Python - Size: 20.5 KB - Last synced: 4 months ago - Pushed: 10 months ago - Stars: 2 - Forks: 0
shobro/ACLA
Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction
Language: Verilog - Size: 47.9 KB - Last synced: 28 days ago - Pushed: about 2 years ago - Stars: 11 - Forks: 2
Po-Chun-Chien/LUT-Net 📦
An implementation of LUT-Net learning procedure
Language: Python - Size: 53.7 KB - Last synced: 4 months ago - Pushed: 10 months ago - Stars: 4 - Forks: 0
asyncvlsi/chp2prs
Automated conversion from CHP to PRS using syntax-directed translation
Language: C++ - Size: 5.56 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 7 - Forks: 5
atul-khobragade/Digital-Logic-Synthesis
To generate an electrical circuit from the given input and output boolean values.
Language: Python - Size: 2.93 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0
scale-lab/BLASYS
An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
Language: Verilog - Size: 16.1 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 21 - Forks: 13
scale-lab/OpenPhySyn
EDA physical synthesis optimization kit
Language: Verilog - Size: 134 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 46 - Forks: 9
scale-lab/BACS
Benchmarks for Approximate Circuit Synthesis
Language: Verilog - Size: 12.8 MB - Last synced: 7 months ago - Pushed: almost 4 years ago - Stars: 13 - Forks: 7
nbulsi/also
A logic synthesis tool
Language: C++ - Size: 2.19 MB - Last synced: 7 months ago - Pushed: over 1 year ago - Stars: 60 - Forks: 30
NYU-MLDA/OpenABC
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
Language: Verilog - Size: 23.7 MB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 62 - Forks: 13
scale-lab/ABACUS
ABACUS is a tool for approximate logic synthesis
Language: C - Size: 4.22 MB - Last synced: 7 months ago - Pushed: almost 4 years ago - Stars: 9 - Forks: 5
NTU-ALComLab/ext-folding 📦
A circuit folding interface in ABC system
Language: C++ - Size: 1.15 MB - Last synced: 9 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0
hriener/lorina
C++ parsing library for simple formats used in logic synthesis and formal verification
Language: C++ - Size: 1.09 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 28 - Forks: 17
The-OpenROAD-Project-Attic/abc Fork of berkeley-abc/abc 📦
Implementing physical synthesis and SDC support into ABC
Language: C - Size: 40.6 MB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 7 - Forks: 4
scale-lab/DRiLLS
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
Language: Python - Size: 418 KB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 73 - Forks: 26
scale-lab/DRUM
The Verilog source code for DRUM approximate multiplier.
Language: Verilog - Size: 83 KB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 25 - Forks: 10
ieee-ceda-datc/RDF-2019
DATC RDF
Language: Verilog - Size: 74.4 MB - Last synced: 12 months ago - Pushed: almost 4 years ago - Stars: 38 - Forks: 11
SJTU-ECTL/MECALS
An approximate logic synthesis tool under the maximum error constraint
Language: Verilog - Size: 219 MB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0
SJTU-ECTL/HEDALS
Highly efficient delay-driven approximate logic synthesis
Language: Verilog - Size: 5.74 MB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 2 - Forks: 0
SJTU-ECTL/VECBEE
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
Language: C++ - Size: 107 MB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 7 - Forks: 3
anthonyabeo/digital_circuits
A collection of digital logic circuits
Language: SystemVerilog - Size: 54.7 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 5 - Forks: 3
NikolaosGian/VLSI-ASIC-IC
An application using Cadence IC Package
Language: Verilog - Size: 9.69 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0
Koyama-Tsubasa/Advanced_Logic_Synthesis
Coursework of NTHU CS613200 Advanced Logic Synthesis
Language: C++ - Size: 10.3 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0
boschmitt/losys
Logic synthesis and verification framework
Language: C++ - Size: 285 KB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 2 - Forks: 0
boschmitt/exorcism
Fast Heuristic Minimization of Exclusive-Sums-of-Products
Language: C++ - Size: 29.3 KB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 4 - Forks: 0
nlwmode/Awesome-Logic-Synthesis
A collection of the Logic Synthesis about peoples/papers/projects/tutorials...
Size: 1.95 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 8 - Forks: 0
Daikon-Sun/FRAIG
Functionally Reduced And-Inverter Graph
Language: C++ - Size: 14.3 MB - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 6 - Forks: 0
porglezomp/minecraft-eda
Electronic design automation for Minecraft
Language: Python - Size: 7.81 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 4 - Forks: 0
born-2learn/DRiLLS Fork of scale-lab/DRiLLS
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization
Size: 407 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 1 - Forks: 0
hriener/aig
C++ header-only And-Inverter graph (AIG) library
Language: C++ - Size: 162 KB - Last synced: about 1 year ago - Pushed: about 6 years ago - Stars: 1 - Forks: 0
reity/article-permutation-circuit-synthesis
This article describes how embedded languages and recursion can be used to create a tool that synthesizes a relatively efficient logical circuit for any chosen permutation of the set of all bit vectors of some fixed length.
Language: Jupyter Notebook - Size: 5.86 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 0 - Forks: 0
porglezomp/nangate
Yosys passes to syntheize to NaN gates (Ã la http://tom7.org/nand/)
Language: C++ - Size: 2.93 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 6 - Forks: 0
raescartin/Recompiler
An approach to algorithm optimization through circuit minimization techniques.
Language: Java - Size: 2.54 MB - Last synced: 4 months ago - Pushed: about 7 years ago - Stars: 0 - Forks: 0
