workcraft/workcraft

Toolset to capture, simulate, synthesize and verify graph models

Language: Java - Size: 74.6 MB - Last synced at: about 7 hours ago - Pushed at: about 7 hours ago - Stars: 65 - Forks: 142

cda-tum/fiction

An open-source design automation framework for Field-coupled Nanotechnologies

Language: C++ - Size: 19 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 71 - Forks: 27

TotoroTron/place-and-route

MS Technical Paper - A study on placement algorithms for heterogeneous FPGAs.

Language: Verilog - Size: 2.72 GB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 2

marcelwa/aigverse

A Python library for working with logic networks, synthesis, and optimization.

Language: Python - Size: 955 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 21 - Forks: 3

nbulsi/also

A logic synthesis tool

Language: C++ - Size: 25.6 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 74 - Forks: 33

marcelwa/ls4ai

Hack4Her: Logic Synthesis for AI

Language: Jupyter Notebook - Size: 46.9 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 5 - Forks: 0

LP-RG/subxpat

The SubXPAT approximate logic synthesis framework

Language: Python - Size: 8.1 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 6 - Forks: 0

The-OpenROAD-Project/yosys Fork of YosysHQ/yosys

Logic synthesis and ABC based optimization

Language: C++ - Size: 28.2 MB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 49 - Forks: 45

changmg/ResubALS

Efficient resubstitution-based approximate logic synthesis

Language: C++ - Size: 4.17 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 6 - Forks: 0

msoeken/cirkit

A circuit toolkit

Language: C++ - Size: 15.8 MB - Last synced at: 6 days ago - Pushed at: over 5 years ago - Stars: 102 - Forks: 38

lsils/kitty

C++ truth table library

Language: C++ - Size: 862 KB - Last synced at: 29 days ago - Pushed at: about 1 month ago - Stars: 56 - Forks: 78

imagarchive/rlst

A Redstone Logic Synthesis Tool because Redstone written in VHDL is cool (IN DEVELOPMENT)

Language: C++ - Size: 334 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

panhomyoung/phyLS

A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

Language: C++ - Size: 32.2 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 26 - Forks: 7

r0nl/HeuristicsBasedLogicSynthesis

Heuristics based approach for Logic Synthesis with the goal to reduce the delay in the circuit and the execution time.

Language: C - Size: 25 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

hriener/lorina

C++ parsing library for simple formats used in logic synthesis and formal verification

Language: C++ - Size: 1.09 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 36 - Forks: 20

hriener/easy

C++ header-only ESOP library

Language: C++ - Size: 1.87 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 5

boschmitt/exorcism

Fast Heuristic Minimization of Exclusive-Sums-of-Products

Language: C++ - Size: 29.3 KB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 6 - Forks: 0

lsils/lstools-showcase

Showcase examples for EPFL logic synthesis libraries

Language: CSS - Size: 21.2 MB - Last synced at: 4 days ago - Pushed at: about 1 year ago - Stars: 194 - Forks: 33

asyncvlsi/chp2prs

Automated conversion from CHP to PRS using syntax-directed translation

Language: C++ - Size: 5.57 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 7 - Forks: 6

scale-lab/DRiLLS

DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

Language: Python - Size: 418 KB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 112 - Forks: 35

clin99/awesome-eda

Size: 51.8 KB - Last synced at: 4 days ago - Pushed at: about 6 years ago - Stars: 92 - Forks: 16

Kevin-Pottier/SOCN

Design and implementation of an ASIC with an 8051 microcontroller core. Includes VHDL modules, C applications, RTL simulations, and mixed-signal validation. Focused on hardware-software co-design and optimization.

Language: VHDL - Size: 1.96 MB - Last synced at: 3 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

lkuresevic/reinforcement_learning_in_logic_synthesis

(WIP) Training an RL model to produce synthesis recipes for logic optimization.

Language: Python - Size: 101 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 0

Ritvik2103/vending-machine-design

Vending Machine Design using Verilog HDL built and tested in Vivado Design Suite

Language: Verilog - Size: 161 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

BUPTslb/LIMGEN

This project will be the beginning of my research life!

Language: C++ - Size: 29.1 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

cornell-zhang/HOGA

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

Language: Python - Size: 635 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 21 - Forks: 2

lnis-uofu/LSOracle

IDEA project source files

Language: Verilog - Size: 547 MB - Last synced at: 11 months ago - Pushed at: over 2 years ago - Stars: 94 - Forks: 42

AlishKanani/ACA-CSU_Approximate-Adders

MATLAB and HDL models of ACA-CSU approximate adders

Language: Verilog - Size: 1.5 MB - Last synced at: 9 months ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 2

NYU-MLDA/OpenABC

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

Language: Verilog - Size: 26.8 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 103 - Forks: 19

snowkylin/npn

A boolean matcher that computes the NPN canonical representative for a given boolean function.

Language: C++ - Size: 20.5 KB - Last synced at: 23 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 2

porglezomp/nangate

Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)

Language: C++ - Size: 2.93 KB - Last synced at: 3 months ago - Pushed at: about 6 years ago - Stars: 7 - Forks: 0

NYU-MLDA/ALMOST

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning

Language: Verilog - Size: 74.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

NYU-MLDA/ABC-RL

This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

Language: Verilog - Size: 21.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

porglezomp/minecraft-eda

Electronic design automation for Minecraft

Language: Python - Size: 7.81 KB - Last synced at: about 2 months ago - Pushed at: about 6 years ago - Stars: 9 - Forks: 0

animeshbchowdhury/RTL_dataset

Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys

Language: Verilog - Size: 6.92 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

NTU-ALComLab/IWLS2021 📦

Code repository for the IWLS 2021 Programming Contest

Language: Python - Size: 602 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 1

Po-Chun-Chien/FringeDT 📦

An implementation of binary decision tree with fringe-features extraction.

Language: Python - Size: 20.5 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

shobro/ACLA

Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction

Language: Verilog - Size: 47.9 KB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 2

Po-Chun-Chien/LUT-Net 📦

An implementation of LUT-Net learning procedure

Language: Python - Size: 53.7 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 4 - Forks: 0

atul-khobragade/Digital-Logic-Synthesis

To generate an electrical circuit from the given input and output boolean values.

Language: Python - Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

hriener/aig

C++ header-only And-Inverter graph (AIG) library

Language: C++ - Size: 162 KB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

scale-lab/BLASYS

An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization

Language: Verilog - Size: 16.1 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 21 - Forks: 13

scale-lab/OpenPhySyn

EDA physical synthesis optimization kit

Language: Verilog - Size: 134 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 46 - Forks: 9

scale-lab/BACS

Benchmarks for Approximate Circuit Synthesis

Language: Verilog - Size: 12.8 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 13 - Forks: 7

scale-lab/ABACUS

ABACUS is a tool for approximate logic synthesis

Language: C - Size: 4.22 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 9 - Forks: 5

NTU-ALComLab/ext-folding 📦

A circuit folding interface in ABC system

Language: C++ - Size: 1.15 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

The-OpenROAD-Project-Attic/abc Fork of berkeley-abc/abc 📦

Implementing physical synthesis and SDC support into ABC

Language: C - Size: 40.6 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 4

scale-lab/DRUM

The Verilog source code for DRUM approximate multiplier.

Language: Verilog - Size: 83 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 25 - Forks: 10

ieee-ceda-datc/RDF-2019

DATC RDF

Language: Verilog - Size: 74.4 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 38 - Forks: 11

SJTU-ECTL/MECALS

An approximate logic synthesis tool under the maximum error constraint

Language: Verilog - Size: 219 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

SJTU-ECTL/HEDALS

Highly efficient delay-driven approximate logic synthesis

Language: Verilog - Size: 5.74 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

SJTU-ECTL/VECBEE

VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis

Language: C++ - Size: 107 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 3

anthonyabeo/digital_circuits

A collection of digital logic circuits

Language: SystemVerilog - Size: 54.7 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 3

NikolaosGian/VLSI-ASIC-IC

An application using Cadence IC Package

Language: Verilog - Size: 9.69 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Koyama-Tsubasa/Advanced_Logic_Synthesis

Coursework of NTHU CS613200 Advanced Logic Synthesis

Language: C++ - Size: 10.3 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

boschmitt/losys

Logic synthesis and verification framework

Language: C++ - Size: 285 KB - Last synced at: about 1 month ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

nlwmode/Awesome-Logic-Synthesis

A collection of the Logic Synthesis about peoples/papers/projects/tutorials...

Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 0

Daikon-Sun/FRAIG

Functionally Reduced And-Inverter Graph

Language: C++ - Size: 14.3 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 0

born-2learn/DRiLLS Fork of scale-lab/DRiLLS

DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization

Size: 407 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

reity/article-permutation-circuit-synthesis

This article describes how embedded languages and recursion can be used to create a tool that synthesizes a relatively efficient logical circuit for any chosen permutation of the set of all bit vectors of some fixed length.

Language: Jupyter Notebook - Size: 5.86 KB - Last synced at: 4 months ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

raescartin/Recompiler

An approach to algorithm optimization through circuit minimization techniques.

Language: Java - Size: 2.54 MB - Last synced at: over 1 year ago - Pushed at: about 8 years ago - Stars: 0 - Forks: 0