ai4co/rl4co

A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)

Language: Python - Size: 51.5 MB - Last synced: about 5 hours ago - Pushed: about 7 hours ago - Stars: 271 - Forks: 54

efabless/nix-eda

Nix derivations for EDA tools

Language: Nix - Size: 87.9 KB - Last synced: 5 days ago - Pushed: 6 days ago - Stars: 2 - Forks: 0

NYU-MLDA/ABC-RL

This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

Language: Verilog - Size: 21.1 MB - Last synced: 11 days ago - Pushed: 11 days ago - Stars: 1 - Forks: 0

shages/liberty-parse

Liberty format parser

Language: Rust - Size: 34.2 KB - Last synced: 12 days ago - Pushed: 19 days ago - Stars: 7 - Forks: 4

sudharavali/Implementation-and-Reduction-of-Reduced-order-Binary-Decision-Diagrams-

Language: Java - Size: 916 KB - Last synced: 12 days ago - Pushed: almost 6 years ago - Stars: 1 - Forks: 1

OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Language: Verilog - Size: 329 MB - Last synced: 12 days ago - Pushed: 12 months ago - Stars: 515 - Forks: 144

byuccl/spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Language: Python - Size: 46 MB - Last synced: 13 days ago - Pushed: 3 months ago - Stars: 85 - Forks: 19

arc-research-lab/CHARM

CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture

Language: C++ - Size: 152 MB - Last synced: 28 days ago - Pushed: 28 days ago - Stars: 99 - Forks: 14

ahmed-agiza/EDAViewer

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Language: JavaScript - Size: 3.09 MB - Last synced: 25 days ago - Pushed: over 1 year ago - Stars: 65 - Forks: 12

madworx/robotframework-kicadlibrary

Robot Framework KiCad Library

Language: Python - Size: 222 KB - Last synced: 18 days ago - Pushed: over 1 year ago - Stars: 8 - Forks: 2

OpenTimer/Parser-Verilog

A Standalone Structural Verilog Parser

Language: Verilog - Size: 6.29 MB - Last synced: about 1 month ago - Pushed: about 2 years ago - Stars: 73 - Forks: 32

cornell-zhang/HOGA

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

Language: Python - Size: 488 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 17 - Forks: 0

najaeda/naja-verilog

A standalone structural (gate-level) verilog parser

Language: C++ - Size: 193 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 20 - Forks: 1

byuccl/spydrnet-tmr

TMR utilities for the SpyDrNet project

Language: Python - Size: 10.7 MB - Last synced: 13 days ago - Pushed: 7 months ago - Stars: 4 - Forks: 2

Lawrence-Leung/YogurtNet

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.

Language: Python - Size: 632 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 1 - Forks: 1

LukeVassallo/RL_PCB

RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).

Language: Python - Size: 15.9 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 5 - Forks: 1

soumilheble/Eagle_Libraries

EAGLE Library for Custom and Special Electrical/Electronic Components

Size: 18.9 MB - Last synced: 3 months ago - Pushed: over 5 years ago - Stars: 1 - Forks: 1

purdue-onchip/gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

Language: C++ - Size: 4.69 MB - Last synced: 3 months ago - Pushed: about 1 year ago - Stars: 94 - Forks: 19

OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Language: C++ - Size: 63.4 MB - Last synced: 3 months ago - Pushed: almost 2 years ago - Stars: 48 - Forks: 23

arc-research-lab/AIM

AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!

Language: C++ - Size: 396 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 18 - Forks: 2

luckyrantanplan/nthu-route

VLSI EDA Global Router

Language: C++ - Size: 11.6 MB - Last synced: 3 months ago - Pushed: over 6 years ago - Stars: 57 - Forks: 12

shobro/ACLA

Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction

Language: Verilog - Size: 47.9 KB - Last synced: 27 days ago - Pushed: about 2 years ago - Stars: 11 - Forks: 2

LQY404/EDA-info

the awesome work, project and lab of EDA (Electronic Design Automation). continue update...

Size: 81.1 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 2 - Forks: 1

NTU-LaDS-II/FAN_ATPG

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Language: Verilog - Size: 10.7 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 51 - Forks: 11

EDAAC/EDAAC

EDA Analytics Central

Language: Python - Size: 232 KB - Last synced: 6 months ago - Pushed: over 1 year ago - Stars: 12 - Forks: 8

matthschw/eda-acronyms

Electronic Design Automation (EDA) Acronyms

Language: TeX - Size: 1.97 MB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 1 - Forks: 0

scale-lab/EDAonCloud

Characterizing and Optimizing EDA Flows for the Cloud (DATE'2021 and TCAD)

Language: Python - Size: 42.4 MB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 7 - Forks: 5

ycchen218/EDA-IRdrop-Prediction

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.

Language: Python - Size: 6.31 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 3 - Forks: 0

erihsu/tf-parser

Technology file parser in Rust

Language: Rust - Size: 94.7 KB - Last synced: 3 days ago - Pushed: about 3 years ago - Stars: 9 - Forks: 2

ycchen218/EDA-Congestion-Prediction

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.

Language: Python - Size: 60.3 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

kanndil/PathView

Language: HTML - Size: 8.05 MB - Last synced: 12 months ago - Pushed: 12 months ago - Stars: 0 - Forks: 0

fakerbaby/Flora

Flora is an new GNN-based Open Source tool can apply to Dreamplace post-processing, so that can achieve faster and more accurate layout design.

Language: Python - Size: 9.89 MB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 3 - Forks: 1

eda-ricercatore/research-contests

A repository for research contests spanning topics from hardware security and embedded/VLSI machine learning to electronic design automation, bio design automation, and formal verification.

Language: TeX - Size: 466 KB - Last synced: 4 months ago - Pushed: about 3 years ago - Stars: 4 - Forks: 1

alkgrove/partlocater

Find a part on Digi-Key and import parameters into local database

Language: Python - Size: 1.55 MB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 14 - Forks: 3

The-OpenROAD-Project/EDAAC Fork of EDAAC/EDAAC

EDA Analytics Central

Language: Python - Size: 214 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 5 - Forks: 4

Rob382/salidas-programables-mejora-de-auto-alarma-

En este proyecto yo hice el rediseño (electrónico y programas), así como modificaciones del sistema de auto alarma previamente implementado por la empresa, solucionando los problemas de consumo de energía y mejorando el circuito funcional (la parte automática) con un rediseño total.

Language: C++ - Size: 6.19 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0

become-iron/basil-eda 📦

Web EDA :leaves:

Language: Vue - Size: 20.5 KB - Last synced: about 1 year ago - Pushed: almost 5 years ago - Stars: 1 - Forks: 1

cuhk-eda/split-extract

Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation

Language: C++ - Size: 1020 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 2 - Forks: 2

poshtkohi/jpad

A Java-based EDA tool for analogue integrated circuit design

Language: Java - Size: 537 KB - Last synced: 11 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

c0rp3n/cento

An implementation of John K. Outsterhout's Corner Stiching.

Language: C++ - Size: 89.8 KB - Last synced: 4 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

electronics-and-drives/MLCAD22

Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"

Size: 1.95 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 2 - Forks: 1

abhinuvpitale/ROBDD

Implementation of ROBDD in python

Language: Jupyter Notebook - Size: 1.19 MB - Last synced: 10 months ago - Pushed: about 6 years ago - Stars: 2 - Forks: 1

YuanTingHsieh/ITDP

Incremental Timing-Driven Placement, problem C of ICCAD contest 2015

Language: C++ - Size: 12.1 MB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 5 - Forks: 2

stevenlowery011/pymensor

Python driver for Mensor Modular Pressure Controllers

Language: Python - Size: 22.5 KB - Last synced: 26 days ago - Pushed: over 4 years ago - Stars: 2 - Forks: 2

YuanTingHsieh/ColorBalancing

Color Balancing for Double Patterning, problem E of CAD contest 2015

Language: C++ - Size: 646 KB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 2 - Forks: 2