GitHub topics: vlsi-testing
Mummanajagadeesh/4-bit-ripple-carry-adder
VLSI test project: 4-bit ripple carry adder with random stuck-at fault injection. Supports ATPG-based verification, fault modeling, and simulation for learning and experimentation
Language: Python - Size: 9.77 KB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0
InnisChen/STRAIT-Self-Test-and-Self-Recovery-for-AI-Accelerator
This is my senior project. Aims to implement the AI accelerator self-test and self-recovery architecture proposed in the paper "STRAIT: Self-Test and Self-Recovery for AI Accelerator". STRAIT is a unified solution that provides self-test, self-diagnosis, and self-recovery functions for systolic array-based AI accelerators.
Language: Verilog - Size: 13.6 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
NTU-LaDS-II/FAN_ATPG
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Language: Verilog - Size: 11.8 MB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 92 - Forks: 12
Saeed-dev2/Saeed-dev2
Config files for my GitHub profile.
Size: 24.4 KB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0
Sukriti-sood/Test-Pattern-Generator
Algorithm for generating test pattern for fault detection.
Language: Python - Size: 30.3 KB - Last synced at: 6 months ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
saikaryekar/Chip-Orientation-Estimation-with-OpenCV
This project focuses on chip orientation estimation using computer vision techniques in a VLSI testing environment. The provided Python script uses OpenCV to create a bounding box around objects in a given image and returns the angular offset of the objects with notations.
Language: MATLAB - Size: 386 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
