GitHub topics: stuck-at-faults
NikosDelijohn/finjenv
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
Language: Verilog - Size: 599 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
kanndil/PODEM-ATPG
Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).
Language: Python - Size: 112 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
cad-polito-it/r4ves
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
Language: Verilog - Size: 4.07 MB - Last synced at: 25 days ago - Pushed at: 11 months ago - Stars: 1 - Forks: 1
agarwalharshal/Automatic_Test_Pattern_Generation
Generation of test pattern or input vector for a given circuit consisting of stuck-at faults and to also determine the expected output. Submitted as part of the Grand Finale of Google Girl Hackathon 2023.
Language: C++ - Size: 11.7 KB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
thnguyen996/fault-injection
Implementation of "Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks." 2021 58th ACM/IEEE Design Automation Conference (DAC).
Language: Python - Size: 137 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 6 - Forks: 0
