hsluoyz/Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

Language: Verilog - Size: 33.1 MB - Last synced: 24 days ago - Pushed: 24 days ago - Stars: 69 - Forks: 34

AUCOHL/Fault

A complete open-source design-for-testing (DFT) Solution

Language: Swift - Size: 4.21 MB - Last synced: about 1 month ago - Pushed: 2 months ago - Stars: 115 - Forks: 24

Coloquinte/quaigh

Logic circuit analysis and optimization

Language: Rust - Size: 258 KB - Last synced: about 1 month ago - Pushed: 4 months ago - Stars: 10 - Forks: 0

UTehran-NavabiLab/SAYAC-system-Testing

Post-manufacturing test analysis

Language: VHDL - Size: 8.72 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0

brahad316/FAN-ATPG

an implementation of the FAN ATPG algorithm in c++ and verilog.

Language: C++ - Size: 9.77 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

xinoip/verilog-atpg

Generate ATPG for fault detection on Verilog circuits. C++/QT

Language: Verilog - Size: 3.5 MB - Last synced: 6 months ago - Pushed: almost 2 years ago - Stars: 5 - Forks: 0

NTU-LaDS-II/FAN_ATPG

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Language: Verilog - Size: 10.7 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 51 - Forks: 11

atvatsal/tiny-faults

Simple EDA tool for fault reduction and testing for combinational circuits

Language: Python - Size: 2.35 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

kalexio/fault-simulator

Simple fault simulator

Language: C - Size: 99.6 KB - Last synced: 9 months ago - Pushed: almost 3 years ago - Stars: 5 - Forks: 0

pfnet-research/ATPG4SV

A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.

Language: OCaml - Size: 40 KB - Last synced: over 1 year ago - Pushed: over 5 years ago - Stars: 12 - Forks: 2

celine-hsieh/VLSI-Testing-LAB-2

Language: Verilog - Size: 1.84 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

celine-hsieh/VLSI-Testing-LAB-1

Fault Simulation | Parallel Fault Simulation | Deductive fault Simulation | Test Coverage

Language: Verilog - Size: 10.1 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

shahsaumya00/D-Algorithm-Combinational

Combinational ATPG generator based on D-Algorithm

Language: C++ - Size: 394 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 11 - Forks: 3

charkster/rpi4_gpio_atpg_stuck_at

Raspberry Pi 4 is used to drive ATPG stuck-at patterns to an IC. Python is used to drive the patterns and check for expected levels on the scan_out pins (4 chains in this example). A Perl script is used to parse the ATP pattern data into Python lists (I prefer to parse text files using Perl).

Language: Python - Size: 5.85 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0

Luca-Dalmasso/RISCV_LBIST Fork of alessandrolandra/RISCV_LBIST

Design of a BIST module for RISC-V fault testing

Size: 60.2 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 1 - Forks: 0

Mrcuve0/TFT-RI5CY-Assignment

Source files and documentation for the final assignment of the "Testing and Fault Tolerance" course.

Language: Verilog - Size: 31.3 MB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 2 - Forks: 2

Tronax1/VLSI-Testing

Algorithm that extracts a circuit from a netlist and performs fault collapsing

Language: C++ - Size: 40 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 3 - Forks: 1

sjindal1/VLSIProj3

Language: C++ - Size: 323 KB - Last synced: about 1 year ago - Pushed: almost 6 years ago - Stars: 0 - Forks: 0