GitHub topics: d-algorithm
xinoip/verilog-atpg
Generate ATPG for fault detection on Verilog circuits. C++/QT
Language: Verilog - Size: 3.5 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 0
atvatsal/tiny-faults
Simple EDA tool for fault reduction and testing for combinational circuits
Language: Python - Size: 2.35 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
rmhanchate/dvtt-assignments
EC804 Digital VLSI Testing and Testability Assignments.
Language: Python - Size: 16.6 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
shahsaumya00/D-Algorithm-Combinational
Combinational ATPG generator based on D-Algorithm
Language: C++ - Size: 394 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 11 - Forks: 3
