Priyanshumishra77/priyanshu.github.io

Personal website

Language: JavaScript - Size: 3.43 MB - Last synced: about 12 hours ago - Pushed: about 13 hours ago - Stars: 1 - Forks: 1

Functional-Bus-Description-Language/go-fbdl

Functional Bus Description Language compiler front-end written in Go.

Language: Go - Size: 1.23 MB - Last synced: about 20 hours ago - Pushed: 1 day ago - Stars: 0 - Forks: 1

danchitnis/EEsim

A browser-based SPICE circuit simulator

Language: TypeScript - Size: 24.9 MB - Last synced: 1 day ago - Pushed: 2 days ago - Stars: 89 - Forks: 6

DigitalLabIIESTS/VLSI-Front-End

Requirements for VLSI front-end Engineer

Size: 3.1 MB - Last synced: 2 days ago - Pushed: 2 days ago - Stars: 3 - Forks: 1

cuhk-eda/Xplace

Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization

Language: C++ - Size: 81.3 MB - Last synced: 2 days ago - Pushed: 2 days ago - Stars: 79 - Forks: 5

ADolbyB/vlsi-spice-pcbs

A collection of Schematics, PCBs and VLSI work on various platforms

Language: SystemVerilog - Size: 5.81 MB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 0 - Forks: 0

AUCOHL/DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

Language: Verilog - Size: 47 MB - Last synced: 4 days ago - Pushed: 18 days ago - Stars: 123 - Forks: 33

TinyTapeout/xschem-viewer

Online viewer of Xschem schematic files

Language: JavaScript - Size: 981 KB - Last synced: 7 days ago - Pushed: 7 days ago - Stars: 16 - Forks: 0

YosysHQ/padring

A padring generator for ASICs

Language: C++ - Size: 177 KB - Last synced: 8 days ago - Pushed: about 1 year ago - Stars: 22 - Forks: 10

TinyTapeout/gdsii

GDSII file format parser for JavaScript

Language: TypeScript - Size: 148 KB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 0 - Forks: 0

Sandy71004/Adders---VLSI

In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.

Size: 7.81 KB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 0 - Forks: 0

OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Language: Verilog - Size: 329 MB - Last synced: 9 days ago - Pushed: 12 months ago - Stars: 515 - Forks: 144

hsluoyz/Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

Language: Verilog - Size: 33.1 MB - Last synced: 10 days ago - Pushed: 10 days ago - Stars: 69 - Forks: 34

1rsh/EC39004

This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur

Language: Verilog - Size: 4.23 MB - Last synced: 16 days ago - Pushed: 2 months ago - Stars: 0 - Forks: 0

asyncvlsi/actflow

Top-level repository for the ACT EDA flow

Language: Shell - Size: 121 KB - Last synced: 15 days ago - Pushed: 16 days ago - Stars: 16 - Forks: 2

en9inerd/SimAn

Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”

Language: C++ - Size: 4.46 MB - Last synced: 17 days ago - Pushed: 17 days ago - Stars: 9 - Forks: 2

The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language: Python - Size: 833 MB - Last synced: 23 days ago - Pushed: 23 days ago - Stars: 1,176 - Forks: 351

efabless/openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

Language: Python - Size: 30.7 MB - Last synced: 23 days ago - Pushed: 23 days ago - Stars: 129 - Forks: 18

asyncvlsi/act

ACT hardware description language and core tools.

Language: C++ - Size: 4.77 MB - Last synced: 21 days ago - Pushed: 21 days ago - Stars: 92 - Forks: 22

DegateCommunity/Degate

A modern and open-source cross-platform software for chips reverse engineering.

Language: C++ - Size: 658 MB - Last synced: 22 days ago - Pushed: 3 months ago - Stars: 230 - Forks: 28

TobiasKaiser/pydesignflow

Micro-Framework for FPGA / VLSI Design Flow in Python

Language: Python - Size: 87.9 KB - Last synced: 22 days ago - Pushed: 22 days ago - Stars: 3 - Forks: 2

broccolimicro/floret

A cell generator designed for advanced nodes

Language: C++ - Size: 322 KB - Last synced: 22 days ago - Pushed: 22 days ago - Stars: 1 - Forks: 0

limbo018/DREAMPlace

Deep learning toolkit-enabled VLSI placement

Language: C++ - Size: 18 MB - Last synced: 25 days ago - Pushed: 26 days ago - Stars: 620 - Forks: 185

ahmed-agiza/EDAViewer

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Language: JavaScript - Size: 3.09 MB - Last synced: 22 days ago - Pushed: over 1 year ago - Stars: 65 - Forks: 12

mehadihn/BRACUCSE460

BRACU CSE460 Lab (Summer 2020)

Language: Scheme - Size: 37.8 MB - Last synced: 30 days ago - Pushed: over 3 years ago - Stars: 3 - Forks: 0

broccolimicro/scripts

One-off scripts that haven't been integrated into a larger flow yet

Language: Python - Size: 37.1 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

the-pinbo/EC302-VLSI-design-lab-

EC302-VLSI-Design-Lab

Language: Roff - Size: 4.3 MB - Last synced: about 1 month ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

the-pinbo/EC704-VLSI-Design-Automation

EC704 - VLSI Design Automation

Language: Jupyter Notebook - Size: 14.2 MB - Last synced: about 1 month ago - Pushed: about 1 year ago - Stars: 0 - Forks: 1

ceciliacsilva/euler-vlsi

Euler-path to stick diagrams - VLSI

Language: Racket - Size: 82 KB - Last synced: 29 days ago - Pushed: over 7 years ago - Stars: 1 - Forks: 1

antonblanchard/vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Language: Python - Size: 3.02 MB - Last synced: 24 days ago - Pushed: 8 months ago - Stars: 100 - Forks: 9

phoeniX-Digital-Design/phoeniX

phoeniX RISC-V Processor

Language: Verilog - Size: 145 MB - Last synced: about 1 month ago - Pushed: about 2 months ago - Stars: 41 - Forks: 5

ojasvi-shah/Advanced-Physical-Design-Using-OpenLANE--Ojasvi-Shah

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

Size: 262 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 2 - Forks: 0

AdarshMishra26/SCL-Project

This is the Repository which contains the detail of my work done at SCL Mohali (formerly Department of Space, ISRO). This was the internship basically focused on the "Experimental Analysis of MOS Capacitor for Oxide Furnaces" and further study of VLSI.

Language: HTML - Size: 3.27 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 2 - Forks: 0

andreaskuster/black-parrot-branch-predictor

Branch Predictor Optimization for BlackParrot

Language: HTML - Size: 220 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 13 - Forks: 8

charlie2951/vlsi

Theory and laboratory practices related to VLSI Design

Size: 146 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Language: VHDL - Size: 4.96 MB - Last synced: about 1 month ago - Pushed: over 3 years ago - Stars: 511 - Forks: 95

asyncvlsi/AMC

AMC: Asynchronous Memory Compiler

Language: Python - Size: 3.14 MB - Last synced: about 2 months ago - Pushed: almost 4 years ago - Stars: 42 - Forks: 11

AUCOHL/OGRE

Global Router Built for ICCAD Contest 2019

Language: C++ - Size: 69.6 MB - Last synced: 22 days ago - Pushed: about 4 years ago - Stars: 28 - Forks: 13

Zhuohao-Li/VLSI-course-note

This repo contains my notes on MR322 2022 Spring at Shanghai Jiao Tong Univ.

Language: VHDL - Size: 37.5 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1 - Forks: 2

purdue-onchip/gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

Language: C++ - Size: 4.69 MB - Last synced: 3 months ago - Pushed: about 1 year ago - Stars: 94 - Forks: 19

nelzeg/stdcell-library

A 12-track height standard cell library built in SKY130 PDK. The cells were designed using Magic VLSI Layout Tool and characterized using Digital Standard Cell Characterizer (DSCC).

Language: Python - Size: 9.44 MB - Last synced: 3 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

nelzeg/stdcell-characterizer

Python-based electronic design automation (EDA) tool for characterizing digital standard cells designed in SKY130 PDK. The characterization process is based in the Synopsys Liberty User Guides and Reference Manual Suite - Version 2017.06

Language: Python - Size: 9.68 MB - Last synced: 3 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

FarshidKeivanian/Minimization-of-Average-Power-Consumption-in-3-Stage-CMOS-Ring-Oscillator-based-on-MSFLA-Fuzzy-MSFL

FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)

Language: MATLAB - Size: 815 KB - Last synced: 3 months ago - Pushed: about 2 years ago - Stars: 1 - Forks: 2

efabless/ravenna

32-bit RISC-V microcontroller

Language: C - Size: 2.14 MB - Last synced: about 2 months ago - Pushed: over 2 years ago - Stars: 11 - Forks: 6

enricomors/cdmo_vlsi

Repo for the project of the course on Combinatorial Decision Making and Optimization @ Unibo

Language: Jupyter Notebook - Size: 29.9 MB - Last synced: 4 months ago - Pushed: 11 months ago - Stars: 0 - Forks: 1

erwanregy/TSMC180-Cell-Library

Digital cell library designed in Magic for the TSMC 180nm process, with an accompanying data book generator script

Language: Python - Size: 114 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

VardhanSuroshi/Vedic-Multiplier-From-RTL2GDS

GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA

Language: Verilog - Size: 6.6 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

VardhanSuroshi/VLSI-ASIC-Design-Flow

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Language: Verilog - Size: 2.93 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 0

broccolimicro/haystack

design and verification of asynchronous circuits

Language: Makefile - Size: 9.73 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

broccolimicro/bcli

A docker container with all of the tools needed for tapeout

Language: Vim Script - Size: 43 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

Brinda15/4-bit-Array-multiplier

An array multiplier using the shift and add algorithm was implemented on LT spice. The gates used in the implementation were built using CMOS logic. An assembly language program was also written to do the same in accordance with the single cycle 32 bit RISC-V processor.

Language: AGS Script - Size: 62.5 KB - Last synced: about 1 month ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

dhruvildarji/MIPS

Made Million Instruction Per Second Processor

Size: 4.74 MB - Last synced: 4 months ago - Pushed: about 6 years ago - Stars: 3 - Forks: 1

briansune/Delta-Sigma-DAC-Verilog

Delta Sigma DAC FPGA

Language: Verilog - Size: 2.78 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 14 - Forks: 4

DigitalLabIIESTS/DigitalDesignUsingVerilogHDL

A Verilog HDL Guide for Beginners.

Language: Verilog - Size: 49.3 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 1

ehw-fit/autoax

Automated tool for approximation of ASIC and FPGA accelerators

Language: C - Size: 696 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 1

masc-ucsc/anubis

The ANUBIS benchmark suite for Incremental Synthesis

Language: C - Size: 33.3 MB - Last synced: about 2 months ago - Pushed: over 3 years ago - Stars: 12 - Forks: 2

Nidhinchandran47/my_rtl_code

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

Language: Verilog - Size: 1.71 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 8 - Forks: 1

celuk/wallace-multiplier-cmos-vlsi

8bit x 8bit Signed Wallace Tree Multiplier 600nm CMOS VLSI Design

Language: Verilog - Size: 154 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

EhsanShahbazii/Digital-VLSI-System-Design-Projects

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

Language: Verilog - Size: 73.2 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 2 - Forks: 0

colepoirier/doug

Doug is a WIP semi-automated to full manual VLSI Analog and Mixed Signal CAD design tool built with Bevy and Layout21

Language: Rust - Size: 27.1 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 14 - Forks: 2

ahirsharan/32-Bit-Floating-Point-Adder

Verilog Implementation of 32-bit Floating Point Adder

Language: Verilog - Size: 458 KB - Last synced: 2 months ago - Pushed: about 4 years ago - Stars: 28 - Forks: 10

OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Language: C++ - Size: 63.4 MB - Last synced: 3 months ago - Pushed: almost 2 years ago - Stars: 48 - Forks: 23

luckyrantanplan/nthu-route

VLSI EDA Global Router

Language: C++ - Size: 11.6 MB - Last synced: 3 months ago - Pushed: over 6 years ago - Stars: 57 - Forks: 12

parangatm/Program-Scheduler

Repository for the course project for EC M216A Design of VLSI Circuits and Systems in Fall 2023 taught by Prof. Dejan Markovic

Language: Verilog - Size: 13.7 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

shobro/ACLA

Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction

Language: Verilog - Size: 47.9 KB - Last synced: 24 days ago - Pushed: about 2 years ago - Stars: 11 - Forks: 2

manili/LDF

Layout Description Framework, a framework to help semi-custom or full-custom designers create the layout of their ICs by writing C# code.

Language: C# - Size: 266 KB - Last synced: 5 months ago - Pushed: almost 2 years ago - Stars: 0 - Forks: 0

mukullokhande99/fifo_hardware_fpga

FIFO implemented on FPGA Spartan 6

Language: Rich Text Format - Size: 21.4 MB - Last synced: 5 months ago - Pushed: almost 3 years ago - Stars: 2 - Forks: 1

stineje/ecen4303F23

Files associated with Digital Integrated Circuits (ecen4303) at Oklahoma State University

Language: Tcl - Size: 23.9 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 9 - Forks: 0

mattrighetti/leiserson-retiming

Python implementation of the Leiserson retiming graph algorithms

Language: Python - Size: 5.13 MB - Last synced: 23 days ago - Pushed: over 3 years ago - Stars: 4 - Forks: 1

imsanjoykb/Electrical-And-Electronic-Engineering-Course-Materials

Electrical And Electronic Engineering Course Materials

Language: MATLAB - Size: 1.68 GB - Last synced: 4 months ago - Pushed: about 2 years ago - Stars: 26 - Forks: 2

Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

Domain Specific Hardware Accelerators - VLSI CAD Project

Language: Bluespec - Size: 4.59 MB - Last synced: 2 months ago - Pushed: over 3 years ago - Stars: 6 - Forks: 2

arm-university/VLSI-Fundamentals-Education-Kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

Language: HTML - Size: 201 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 121 - Forks: 34

ucdrstdenis/cdsAsync

cdsAsync: An Asynchronous VLSI Toolset & Schematic Library

Language: Verilog - Size: 27.7 MB - Last synced: 4 months ago - Pushed: almost 5 years ago - Stars: 24 - Forks: 7

NTU-LaDS-II/FAN_ATPG

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Language: Verilog - Size: 10.7 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 51 - Forks: 11

kabazoka/Wirelength-Driven-Detailed-Macro-Placement-with-Force-Directed-Method

Solution for 2022 ICCAD Problem D: Wirelength Driven Detailed Macro Placemet

Language: C++ - Size: 11.9 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 3 - Forks: 0

harshithsn/SCOAP-Controllability-and-Observability

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs SCOAP Controllability and Observability of circuit..

Language: Jupyter Notebook - Size: 14.6 KB - Last synced: 7 months ago - Pushed: over 2 years ago - Stars: 3 - Forks: 1

harshithsn/Universal-Shift-Register

This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

Language: Verilog - Size: 128 KB - Last synced: 7 months ago - Pushed: almost 2 years ago - Stars: 7 - Forks: 1

harshithsn/Fault-collapsing-and-Fault-simulation

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsing, Parallel fault simulation, Deductive fault simulation.

Language: Jupyter Notebook - Size: 6.12 MB - Last synced: 7 months ago - Pushed: over 2 years ago - Stars: 4 - Forks: 2

the-pinbo/ROBDD

A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.

Language: Jupyter Notebook - Size: 5.39 MB - Last synced: about 1 month ago - Pushed: over 1 year ago - Stars: 2 - Forks: 1

Sh14345/CMOS-using-LTspice

This repository contains a CMOS inverter circuit designed and simulated using LTspice. A CMOS inverter which is actually a "Hello World" in VLSI design logic is a fundamental building block in digital electronics, and this project aims to showcase its operation and characteristics.

Language: AGS Script - Size: 15.6 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 0 - Forks: 0

ucerd/Summer-School-2023_2

Summer School on Full Stack Open-Source Ecosystem for Processor Based Chip Design

Size: 59.3 MB - Last synced: 4 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

phoeniX-Digital-Design/.github

Size: 188 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 0

yarpose/YARPOSE.OpenSource_MagicViewer

Open Source Magic Viewer platform-independent in-browsers via CheeprJ. This is a simple one file only magic files viewer in browsers. This includes .class .java and a complete chip to render demo.

Language: Java - Size: 865 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

rodrigowue/LEX

LEX - Spice Standard-cell Arcs Extractor (also extracts boolean expression, truth table, inputs, and outputs)

Language: C++ - Size: 2.89 MB - Last synced: 7 months ago - Pushed: 8 months ago - Stars: 3 - Forks: 1

123-r-ajay/sr_latch

implementing the sr_latch layout

Size: 730 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

eda-rs/netlist

generic NetList data structure for VLSI

Language: Verilog - Size: 17.8 MB - Last synced: 12 days ago - Pushed: 9 months ago - Stars: 5 - Forks: 2

Saptarshi-prog/VLSI-Tspice

This repository contains some the codes to simulate various operations and characteristics of MOS circuits

Language: SourcePawn - Size: 82 KB - Last synced: 8 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 1

QBlobster/true-single-phase-clock

A frequency divider implemented using true single-phase clock (TSPC).

Language: Lex - Size: 2.84 MB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

QBlobster/parallel-prefix-adder

A parallel-prefix adder implemented using Ling’s transformation.

Language: SourcePawn - Size: 1.71 MB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

Chen-yuMau/VLSI-Physical-and-Logic-Design-Automation

This repository include some of the most fundamental concepts of VLSI design automation

Language: C++ - Size: 23.4 KB - Last synced: 6 months ago - Pushed: almost 2 years ago - Stars: 3 - Forks: 1

NishchalAV/Pulse-Generator-250nm_TannerEDA

Using a pulse wave as an input referencing as clock we try to generate three different pulses having different pulse width

Language: SourcePawn - Size: 779 KB - Last synced: 9 months ago - Pushed: 12 months ago - Stars: 0 - Forks: 0

matthschw/bondtools

Toolbox for creating a bonding diagram in Cadence Virtuoso

Language: HCL - Size: 304 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 1 - Forks: 1

matthschw/skill-sch2sym

Transform a Cadence Virtuoso Schematic in a Symbol

Size: 271 KB - Last synced: 9 months ago - Pushed: 12 months ago - Stars: 0 - Forks: 0

matthschw/sch2tikz

schematic to tikzpicture converter for Cadence Virtuoso

Language: TeX - Size: 117 KB - Last synced: 9 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

AmeyaVS/SystemC_DEPRECATED 📦

SystemC Open Source Implementation Clone from Accellera.org

Language: C++ - Size: 21.4 MB - Last synced: 9 months ago - Pushed: almost 6 years ago - Stars: 3 - Forks: 1

mwritescode/VLSI

Solving The VLSI (Very Large Scale Integration) optimization problem using constraint programming and SMT.

Language: Python - Size: 6.24 MB - Last synced: 9 months ago - Pushed: over 2 years ago - Stars: 1 - Forks: 1

nitram2342/degate 📦

Open source software for chip reverse engineering.

Language: C++ - Size: 379 MB - Last synced: 7 months ago - Pushed: over 3 years ago - Stars: 166 - Forks: 41

SrikarSiddarth/VLSI-Design-Lab

Contains the codes for simulation of various circuits mentioned in the VLSI Design Lab Course

Size: 6.42 MB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 1 - Forks: 2

stineje/prefix_adders

Prefix adder generators for Verilog

Language: Perl - Size: 59.6 KB - Last synced: 10 months ago - Pushed: almost 3 years ago - Stars: 3 - Forks: 4

atvatsal/tiny-faults

Simple EDA tool for fault reduction and testing for combinational circuits

Language: Python - Size: 2.35 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0