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GitHub / OpenTimer / OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/OpenTimer%2FOpenTimer
Stars: 515
Forks: 144
Open Issues: 55
License: other
Language: Verilog
Repo Size: 329 MB
Dependencies:
0
Created: almost 9 years ago
Updated: 12 days ago
Last pushed: 12 months ago
Last synced: 11 days ago
Topics: cad, circuit-analysis, circuit-simulation, circuit-simulator, computer-aided-design, cpp17, eda, electronic-design-automation, parallel-computing, sta, static-timing-analysis, verilog, vlsi, vlsi-circuits, vlsi-physical-design
Files
No dependencies found