clin99/awesome-eda

Size: 51.8 KB - Last synced at: 13 days ago - Pushed at: over 6 years ago - Stars: 94 - Forks: 17

bravo-t/ToyDelay

An educational delay calculation engine for STA tools

Language: C++ - Size: 206 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

tamrahargus/tamrahargus

Personal GitHub repository for experiments, project tests, and general development work.

Size: 16.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Randy1005/Ink

Incremental k-Critical Path Generation

Language: C++ - Size: 494 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 6 - Forks: 0

OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Language: Verilog - Size: 329 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 633 - Forks: 159

Circuits-and-Systems-Lab-CASlab/UPSET

UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

Language: Verilog - Size: 7.46 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 5 - Forks: 0

Pa1mantri/TCL_Scripting

TCL Script to automate the generation of Pre-layout QoR results

Language: Verilog - Size: 6.38 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

himanshu5-prog/static_timing_analysis

This repo implements VLSI static timing analysis using C++.

Language: C++ - Size: 92.8 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

MalakSadek/StaticTimingAnalyzer

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

Language: HTML - Size: 1.2 MB - Last synced at: 7 months ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 3

Ritvik2103/vending-machine-design

Vending Machine Design using Verilog HDL built and tested in Vivado Design Suite

Language: Verilog - Size: 161 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

kanndil/PathView

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

Language: HTML - Size: 8.05 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 1

Crepopcorn/sta_check_temporary

This project is the script for STA report violated path checks temporarily (not final version due to confidentiality).

Language: C - Size: 25.4 KB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

YubiYubi719/NYCU-Special-Topics-in-Computer-Aided-Design

Language: Verilog - Size: 612 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Language: C++ - Size: 63.4 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 50 - Forks: 23

coherent17/NYCU-Special-Topics-in-Computer-Aided-Design

CAD in NYCU

Language: Verilog - Size: 10.7 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

shobhit-mittra/STA-Review

This project is a part of the report for my 7th semester program elective (EC-4143 VLSI-CAD).

Language: Tcl - Size: 340 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

fayizferosh/yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

Language: Verilog - Size: 1.17 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 12 - Forks: 0

ThunderCarver/Electronic-Design-Automation

A collection of interesting projects in EDA field

Language: Tcl - Size: 58.6 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0