Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: static-timing-analysis

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Language: C++ - Size: 63.4 MB - Last synced: 9 days ago - Pushed: almost 2 years ago - Stars: 48 - Forks: 23

A High-performance Timing Analysis Tool for VLSI Systems

Language: Verilog - Size: 329 MB - Last synced: about 1 month ago - Pushed: about 1 year ago - Stars: 515 - Forks: 144

Incremental k-Critical Path Generation

Language: C++ - Size: 492 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 4 - Forks: 0

Size: 51.8 KB - Last synced: about 2 months ago - Pushed: almost 5 years ago - Stars: 84 - Forks: 19

5-Day TCL begginer to advanced workshop by VSD

Language: Verilog - Size: 6.38 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

CAD in NYCU

Language: Verilog - Size: 10.7 MB - Last synced: 5 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

This project is a part of the report for my 7th semester program elective (EC-4143 VLSI-CAD).

Language: Tcl - Size: 340 KB - Last synced: 4 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

5 Day TCL begginer to advanced training workshop by VSD

Language: Verilog - Size: 1.17 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 12 - Forks: 0

Language: HTML - Size: 8.05 MB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

A collection of interesting projects in EDA field

Language: Tcl - Size: 58.6 KB - Last synced: 11 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

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