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GitHub / ahirsharan / 32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ahirsharan%2F32-Bit-Floating-Point-Adder
Stars: 28
Forks: 10
Open Issues: 5
License: None
Language: Verilog
Repo Size: 458 KB
Dependencies: pending
Created: over 4 years ago
Updated: 5 months ago
Last pushed: about 4 years ago
Last synced: 3 months ago
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