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GitHub topics: vlsi-project

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

SACHINUR17/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 23.4 KB - Last synced at: 24 days ago - Pushed at: 25 days ago - Stars: 1 - Forks: 0

Kethasriramya2912/Btech_Projects

I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.

Language: SystemVerilog - Size: 20.8 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

tharunchitipolu/Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Language: Verilog - Size: 19.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 32 - Forks: 6

harshithsn/SCOAP-Controllability-and-Observability

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs SCOAP Controllability and Observability of circuit..

Language: Jupyter Notebook - Size: 14.6 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 1

harshithsn/Fault-collapsing-and-Fault-simulation

This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsing, Parallel fault simulation, Deductive fault simulation.

Language: Jupyter Notebook - Size: 6.12 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 2

karthik-r-rao/VLSI_Physical_Design_Tool

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

Language: Python - Size: 890 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 3

hibagus/64pointFFTProcessor

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

Language: Verilog - Size: 29.8 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 13 - Forks: 7

gmurro/VLSI

Very Large Scale Integration project for CDMO class at @unibo

Language: Python - Size: 15.1 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 4

tharunchitipolu/SHA-256-Verilog-HDL

SHA-2 (Secure Hash Algorithm 2), of which SHA-256 is a part, is one of the most popular hashing algorithms out there.

Language: Verilog - Size: 12.7 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 1