GitHub topics: rtldesign
Kethasriramya2912/Btech_Projects
I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.
Language: SystemVerilog - Size: 20.8 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
shinowtf/FGPA-RFID-Door-Access-Gate-control-with-DE2-115
This is my University Digital System Assignment which using Verilog HDLCode to code DE2-115 board for RFID access card door control
Language: Verilog - Size: 1.39 MB - Last synced at: about 2 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
princeranjan03/ImageEncryption_I-CHIP
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
Language: Verilog - Size: 7.3 MB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
iammituraj/tweak_circuits
Tweak circuits designed in VHDL/Verilog like CDC synchronizers: Pulse synchronizer, Reset synchronizer, Two-flop synchronizer, Edge detectors, Pulse generators, Clock gating etc.
Language: VHDL - Size: 47.9 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 1
iammituraj/reset_and_cdc_synchronizers
Reset and CDC synchronizers developed in Verilog/System Verilog.
Language: SystemVerilog - Size: 11.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1
avashist003/SystemVerilog_Design_Verification
Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
Language: SystemVerilog - Size: 354 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 16 - Forks: 3
