GitHub topics: dadda-tree
tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Language: Verilog - Size: 19.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 32 - Forks: 6
PaletiKrishnasai/VLSI_Practice
work done as part of VLSI Design practice course
Language: Verilog - Size: 4.3 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 3
Related Keywords
dadda-tree
2
verilog
2
vlsi
2
xilinx
1
wallace-tree-multiplier
1
verilog-parser
1
sklansky-adder
1
ripple-carry-adder
1
register
1
recursive-doubling-cla
1
parity-generator
1
array-multiplication
1
wallace
1
vlsi-project
1
vlsi-design
1
tree-multipliers
1
rtl
1
multiplier
1
hardware-description-language
1
fulladder
1
fast-multiplication
1
dadda-multiplier
1
carry-save-adder
1