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GitHub topics: verilog-parser

Nic30/hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

Language: C++ - Size: 14.5 MB - Last synced at: 3 days ago - Pushed at: 29 days ago - Stars: 299 - Forks: 76

codinuum/cca

Code Continuity Analysis Framework

Language: OCaml - Size: 5.89 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 21 - Forks: 5

PaletiKrishnasai/VLSI_Practice

work done as part of VLSI Design practice course

Language: Verilog - Size: 4.3 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 3

Related Keywords
verilog-parser 3 verilog 2 java-parser 1 ontology 1 python-parser 1 semantic-web 1 software-engineering 1 syntax-aware 1 array-multiplication 1 dadda-tree 1 parity-generator 1 recursive-doubling-cla 1 register 1 ripple-carry-adder 1 sklansky-adder 1 vlsi 1 wallace-tree-multiplier 1 xilinx 1 fortran-parser 1 cpp-parser 1 ast-patching 1 ast-patch-tool 1 ast-matching 1 ast-differencing 1 ast-diff-tool 1 vhdl-parser 1 vhdl 1 systemverilog-parser 1 systemverilog 1 python 1 parser 1 fpga 1 antrl4 1