dohuyminhdung/PQC_Dilithium

Language: SystemVerilog - Size: 98.6 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 3 - Forks: 0

google/qkeras

QKeras: a quantization deep learning library for Tensorflow Keras

Language: Python - Size: 1.57 MB - Last synced at: 13 days ago - Pushed at: 5 months ago - Stars: 576 - Forks: 110

ToNi3141/RasterIX

OpenGL 1.x implementation for FPGAs

Language: C++ - Size: 11.8 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 103 - Forks: 12

Essenceia/Blake2

Blake2 RTL implementation

Language: Verilog - Size: 260 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 3 - Forks: 0

hossein1387/BARVINN

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

Language: Tcl - Size: 8.96 MB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 90 - Forks: 15

Unicamp-Odhin/Rofofo

Audio Processing and AI Acceleration with FPGA

Language: Tcl - Size: 37.1 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 4 - Forks: 0

CIE-PESU/CIE_RISCV_Project

RISC-V K-Nearest Neighbors Accelerator for Image Recognition on FPGA

Language: Assembly - Size: 21.9 MB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 4 - Forks: 1

TurakhiaLab/DP-HLS

HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA

Language: C++ - Size: 111 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 11 - Forks: 2

VonTum/Dedekind

The codebase that computed the Ninth Dedekind Number

Language: C++ - Size: 1.27 MB - Last synced at: 2 months ago - Pushed at: 7 months ago - Stars: 14 - Forks: 4

yasnakateb/VectorOps

🏄 Custom IP for vector operations

Language: VHDL - Size: 540 KB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 0

DAL3X/somewhat-homomorphic-encryption-system

Implementation of a somewhat homomorphic encryption system using an FPGA hardware accelerator. This project was part of my bachelor's thesis at KIT and developed in four months.

Language: C - Size: 22.4 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

jofrfu/tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Language: VHDL - Size: 1.42 MB - Last synced at: 6 months ago - Pushed at: almost 7 years ago - Stars: 465 - Forks: 66

NikhilMukraj/spiking-neural-networks-hardware

An FPGA design for simulating biological neurons

Language: SystemVerilog - Size: 437 KB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 14 - Forks: 0

Er1cZ/Deploying_CNN_on_FPGA_using_OpenCL

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.

Language: Objective-C - Size: 31.7 MB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 109 - Forks: 41

m-spr/RCEHDC

An automated HDC platform

Language: VHDL - Size: 16.2 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 9 - Forks: 5

rockyco/autoDSE

A framework for Automated Design Space Exploration

Language: C++ - Size: 30.3 KB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

twosixlabs/ultrazed_dev

UltraZed Development

Language: C - Size: 93.3 MB - Last synced at: 7 months ago - Pushed at: over 7 years ago - Stars: 7 - Forks: 4

doonny/PipeCNN

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

Language: C - Size: 3.7 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 1,252 - Forks: 369

sarnold/Microzed-PYNQ Fork of FredKellerman/Microzed-PYNQ

Enable PYNQ on the Avnet MicroZed boards

Size: 70.3 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

aliemo/transfomers-silicon-research

Research and Materials on Hardware implementation of Transformer Model

Language: Jupyter Notebook - Size: 1.84 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 183 - Forks: 25

matthiaskonrath/rc4-verilog

EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.

Language: C++ - Size: 169 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 0

SakaSerbia/FPGA-DE10-Standard-Project-Nios2-DMA-Accelerator

Develop DMA acceleration of the system that performs linear computing functions, Y = AX + B, large amounts of data.

Size: 18.6 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

AzazHassankhan/Low_Latency_Hardware_Accelerator_For_StockMarket_Indicators

📈 Welcome to the repository that powers the future of stock market analysis with lightning-fast hardware acceleration on FPGA! ⚡️

Language: Jupyter Notebook - Size: 928 KB - Last synced at: 7 months ago - Pushed at: about 2 years ago - Stars: 4 - Forks: 2

hajin-kim/FPGA_AXI_and_VHDL

FPGA with Xilinx Vitis HLS and ZYNQ board. AXI and VHDL: Simple Multiplier, AXI and VHDL: DoGain

Language: VHDL - Size: 2.41 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

dpretet/bster

Implementation of a binary search tree algorithm in a FPGA/ASIC IP

Language: SystemVerilog - Size: 299 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 12 - Forks: 3

rameloni/soil-segmentation-zcu102

A heterogeneous implementation (SW/HW) of an image processing algorithm running on a Yocto-linux OS

Language: Verilog - Size: 414 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1

RSPwFPGAs/opae-xilinx

OPAE porting to Xilinx FPGA devices.

Language: Coq - Size: 6.66 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 33 - Forks: 13

hajin-kim/FPGA_Tutorial_with_HLS

FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS

Language: Tcl - Size: 4.41 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 0

cameronshinn/tiny-tpu

Small-scale Tensor Processing Unit built on an FPGA

Language: Verilog - Size: 1.93 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 86 - Forks: 17

hsharma35/dnnweaver2

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

Language: Jupyter Notebook - Size: 19.9 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 174 - Forks: 73

ToNi3141/RasteriCEr

Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)

Language: C++ - Size: 3.74 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 10 - Forks: 4

os-hxfan/BayesNN_FPGA

FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.

Language: Python - Size: 89.8 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 9 - Forks: 0

tristynferreiro/ISD-PO

A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.

Language: VHDL - Size: 18.6 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

FloyedShen/mnist_hls

Lenet for MNIST handwritten digit recognition using Vivado hls tool

Language: Objective-C - Size: 2.5 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 31 - Forks: 10

mmattioli/hardware-sort

Hardware-accelerated sorting algorithm

Language: VHDL - Size: 8.79 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 13 - Forks: 4

microdynamics-cpu/tree-core-sim

A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.

Language: C++ - Size: 46.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

SamsungLabs/Butterfly_Acc

The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"

Language: Verilog - Size: 257 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 36 - Forks: 12

ribesstefano/Mapping-Multiple-LSTM-Models-on-FPGAs

Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.

Language: Jupyter Notebook - Size: 8.55 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 0

AhmedERady/Grad_Project

Smart Automation Controller for Precision Agriculture

Language: V - Size: 124 MB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Manwlis/FPGA-accelerated-Hadamard-products-with-threshold 📦

Reconfigurable Digital Systems HRY591-project.

Language: C - Size: 197 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

tirumalnaidu/opencl-hls-cnn-accelerator

OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.

Language: C - Size: 49.5 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 53 - Forks: 10

doctor3w/HLS-Cryptography-Accelerator

A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer

Language: Assembly - Size: 955 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 13 - Forks: 2

lirui-shanghaitech/CNN-Accelerator-VLSI

Convolutional accelerator kernel, target ASIC & FPGA

Language: Verilog - Size: 1.59 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 44 - Forks: 6

hibagus/64pointFFTProcessor

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

Language: Verilog - Size: 29.8 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 13 - Forks: 7

lirui-shanghaitech/A-convolution-kernel-implemented-by-Vivado-HLS

This project implements a convolution kernel based on vivado HLS on zcu104

Language: C++ - Size: 9.12 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 23 - Forks: 7

akzare/HardORB

TCP/IP and UDP/IP protocol stack off-loading

Language: Verilog - Size: 59.6 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 9 - Forks: 1

AnshuTrivedi/Intel-Edge-AI-for-IoT-Developers-Nanodegree-Program

This repository contains detailed notes of all chapters and all three projects completed in Intel-Edge-AI NanoDegree.

Language: Jupyter Notebook - Size: 148 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 2

andrei-ace/yoga-ai

Predicting 3D human pose from single image using a VCK5000 Versal Development Card

Language: C++ - Size: 763 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

systemviewinc/visual-system-integrator

Visual System Integrator - Accelerate your embedded development

Language: Python - Size: 4.88 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 6 - Forks: 4

gsneha26/Darwin-WGA

Co-processor for whole genome alignment

Language: Verilog - Size: 61.7 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 9 - Forks: 4

pedrovt/cr-square-root-cop

A FPGA Based Square Root Approximation Coprocessor

Language: VHDL - Size: 220 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 1

max-exner/TURBOdeb

TURBOdeb #xohw19-157 #TuringBombe #Enigma

Language: Coq - Size: 50.6 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

TurtleTaco/Janus-C-Plus-Plus

Janus Algorithm in C++ version without FPGA acceleration.

Language: Ada - Size: 10.2 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

ieee820/PipeCNN Fork of doonny/PipeCNN

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

Language: C++ - Size: 3.52 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

TurtleTaco/Janus-Simulation

Janus astrophysics Simulator implemented on ZU19EG Ultrascale+

Language: LLVM - Size: 187 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0