GitHub topics: axi

Repositories

SystemRDL/PeakRDL

Control and status register code generator toolchain

Language: Python - Size: 159 KB - Last synced at: 4 days ago - Pushed at: about 1 month ago - Stars: 123 - Forks: 27

hdl-registers/hdl-registers

An open-source HDL register code generator fast enough to run in real time.

Language: Python - Size: 2.22 MB - Last synced at: 11 days ago - Pushed at: 12 days ago - Stars: 59 - Forks: 7

rggen/rggen

Code generation tool for control and status registers

Language: Ruby - Size: 510 KB - Last synced at: 11 days ago - Pushed at: 2 months ago - Stars: 377 - Forks: 46

taichi-ishitani/tvip-axi

AMBA AXI VIP

Language: SystemVerilog - Size: 153 KB - Last synced at: 22 days ago - Pushed at: 10 months ago - Stars: 389 - Forks: 109

Wissance/QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Language: Verilog - Size: 127 KB - Last synced at: 17 days ago - Pushed at: over 7 years ago - Stars: 22 - Forks: 7

pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Language: SystemVerilog - Size: 9.07 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1,238 - Forks: 278

taichi-ishitani/tnoc

Network on Chip Implementation written in SytemVerilog

Language: SystemVerilog - Size: 406 KB - Last synced at: 22 days ago - Pushed at: over 2 years ago - Stars: 171 - Forks: 46

MicroTCA-Tech-Lab/libudmaio

Userspace I/O library for Xilinx AXI S2MM DMA

Language: C++ - Size: 43.6 MB - Last synced at: 9 days ago - Pushed at: about 2 months ago - Stars: 7 - Forks: 2

Kampi/OV7670

FPGA interface and driver for an OV7670 camera sensor.

Language: VHDL - Size: 31.3 KB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.

Language: C - Size: 6.94 MB - Last synced at: 13 days ago - Pushed at: almost 2 years ago - Stars: 8 - Forks: 1

wyvernSemi/mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Language: VHDL - Size: 2.71 MB - Last synced at: 21 days ago - Pushed at: 5 months ago - Stars: 22 - Forks: 3

rggen/rggen-sv-rtl

Common SystemVerilog RTL modules for RgGen

Language: SystemVerilog - Size: 99.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 12 - Forks: 2

RISMicroDevices/OpenNCB 📦

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

Language: Scala - Size: 329 KB - Last synced at: 3 months ago - Pushed at: 6 months ago - Stars: 8 - Forks: 1

olagrottvik/bust

Utility for creating and modifying VHDL bus slave modules

Language: Python - Size: 7.85 MB - Last synced at: 3 days ago - Pushed at: 2 months ago - Stars: 9 - Forks: 1

Fcatilizer/Web-Video-Streaming

A Web Video Streaming Application

Language: JavaScript - Size: 19.8 MB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

hdl-modules/hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Language: VHDL - Size: 2.64 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 120 - Forks: 17

ubyhzargam/AMBA-Protocol-Family

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

Language: Verilog - Size: 4.88 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

SkyVerify/AXI4_VIP

AXI4 Verification IP

Language: SystemVerilog - Size: 1.48 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Mohamed-Ramadan1/Mix-Master

Language: JavaScript - Size: 93.8 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

yasnakateb/VectorOps

🏄 Custom IP for vector operations

Language: VHDL - Size: 540 KB - Last synced at: about 1 month ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

rodrigomelo9/amba

A presentation about Advanced Microcontroller Bus Architecture

Language: SystemVerilog - Size: 3.51 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

ipapal/axi-dma-petalinux

AXI DMA with Petalinux

Size: 8.79 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

pulp-platform/axi_node 📦

AXI X-Bar

Language: SystemVerilog - Size: 187 KB - Last synced at: 5 months ago - Pushed at: about 5 years ago - Stars: 19 - Forks: 35

IlyaChichkov/AXI_Counter

Реализация AXI интерфейса на SystemVerilog

Language: SystemVerilog - Size: 61.5 KB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

opifexM/RSS-Aggregator

RSS Aggregator is a web application that collects, parses, and displays news feeds from various sources, offering a multi-language, user-friendly interface for managing and reading RSS feeds.

Language: JavaScript - Size: 983 KB - Last synced at: about 2 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

ZipCPU/sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Language: Verilog - Size: 7.1 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 146 - Forks: 25

pkill37/asic-linreg

ASIC for executing vectorized gradient descent on linear regression problems.

Language: VHDL - Size: 110 MB - Last synced at: 12 months ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1

Onlynfk/my-spotify-reactjs

Spotify Clone With Reactjs

Language: JavaScript - Size: 619 KB - Last synced at: 12 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

Florin623/AXI-Lite-Slave-FPU-IP

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

Language: VHDL - Size: 142 MB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Florin623/AXI-Lite-Slave-FFT-IP

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

Language: VHDL - Size: 71.2 MB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

AranelLindi/AXI_SpaceWire_IP

Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

Language: VHDL - Size: 59.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

vacagonzalo/soc-workflow-vhdl

Example workflow project for VHDL development.

Language: VHDL - Size: 12.7 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

imhcyx/axi.vh

Verilog header for easier AXI interface declaration & connection

Language: SystemVerilog - Size: 5.86 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

mwrnd/innova2_xcku15p_ddr4_bram_gpio

XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA

Language: Tcl - Size: 6.91 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 12 - Forks: 2

d953i/Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

Language: Tcl - Size: 28.6 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 28 - Forks: 17

pulp-platform/axi2per

AXI to Peripheral Interconnect

Language: SystemVerilog - Size: 36.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 1

RSPwFPGAs/opae-xilinx

OPAE porting to Xilinx FPGA devices.

Language: Coq - Size: 6.66 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 33 - Forks: 13

pothosware/PothosFPGA

Pothos FPGA computational offload and buffer integration support

Language: VHDL - Size: 26.9 MB - Last synced at: about 2 months ago - Pushed at: almost 10 years ago - Stars: 9 - Forks: 1

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

PoliTo-ASAC-Lab/PYNQ_UARTopus

Python platform to use a TUL PYNQ-Z2 development board to virtualize up to 12 UART connections (tx+rx@9600bps) over TCP-IP

Language: Python - Size: 44.4 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

igor-sergeevich-po/affordable-housing

Сервис по подбору доступного жилья.

Language: JavaScript - Size: 9.26 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

gednyengs/dma

Open-Source AXI4 DMA Engine in SystemVerilog and Chisel

Language: Scala - Size: 4.46 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 3

suoglu/AXI-GPIO

Custom AXI GPIO core with up to 32 input and 32 output ports

Language: Tcl - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

narendiran1996/AXILearning

Learning Resources for AXI made by self

Language: VHDL - Size: 6.92 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

mjh-design/DMA-S2MM-and-MM2S Fork of 2cc2ic/DMA-S2MM-and-MM2S

Build an open source, extremely simple DMA.

Size: 165 MB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

mjh-design/AXI_DMA Fork of wanderingnail/AXI_DMA

一个基于AXI的DMA

Size: 2.59 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

mjh-design/AXI_spec_chinese Fork of lizhirui/AXI_spec_chinese

AXI协议规范中文翻译版

Size: 478 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

mjh-design/verilog-axis Fork of alexforencich/verilog-axis

Verilog AXI stream components for FPGA implementation

Size: 1.08 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Related Keywords

axi 68 fpga 30 xilinx 17 verilog 16 systemverilog 14 amba 12 vhdl 12 vivado 11 asic 9 rtl 8 axi4 7 dma 6 apb 6 xilinx-vivado 5 xilinx-fpga 5 hardware 5 soc 5 ip 5 axi-lite 5 uvm 5 axi-stream 4 zynq 4 eda 4 vitis 4 react 3 microblaze 3 verilog-components 3 pcie 3 chisel 3 amba-axi 3 tcl 3 react-router 3 uart 3 c 3 pynq-z2 3 python 3 csr 3 ahb 3 communication-protocol 3 c-programming 2 network-on-chip 2 register-descriptions 2 xdma 2 fpga-soc 2 avalon 2 systemverilog-hdl 2 verilator 2 nextjs 2 axis 2 hdl 2 fpga-accelerator 2 reactjs 2 fifo 2 generator 2 arm 2 uvm-register-model 2 pipeline 2 wishbone-bus 2 processor 2 altera 2 microelectronics 2 master-slave 2 interconnect 2 intellectual-property 2 integrated-circuits 2 spi 2 pynq-z1 2 design 2 digital 2 pynq-hardware-overlay 2 spi-interface 2 pynq 2 ddr4 2 electronics 2 jupyter-notebook 2 artix-7 1 axi-memory-mapped 1 basys3 1 innova-2-flex 1 vivado-vitis 1 embedded 1 01pg974 1 pcie-xdma 1 hls 1 innova2 1 vivado-ip-integrator 1 mnv303212a-adlt 1 vitis-hls 1 4xc7a16683 1 mnv303212a 1 xcku15p 1 dimm 1 mig 1 rdimm 1 ddr 1 sodimm 1 sqrl 1 udimm 1 vcu1525 1 csv 1