GitHub topics: wishbone-bus
pbing/ibex_wb
RISC-V Ibex core with Wishbone B4 interface
Language: SystemVerilog - Size: 1.19 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 15 - Forks: 4

rggen/rggen
Code generation tool for control and status registers
Language: Ruby - Size: 510 KB - Last synced at: 3 days ago - Pushed at: 3 months ago - Stars: 381 - Forks: 46

ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Language: Verilog - Size: 15.1 MB - Last synced at: 22 days ago - Pushed at: 4 months ago - Stars: 273 - Forks: 43

ZipCPU/wb2axip
Bus bridges and other odds and ends
Language: Verilog - Size: 8.78 MB - Last synced at: 22 days ago - Pushed at: 30 days ago - Stars: 544 - Forks: 110

ZipCPU/wbscope
A wishbone controlled scope for FPGA's
Language: Verilog - Size: 758 KB - Last synced at: 22 days ago - Pushed at: over 1 year ago - Stars: 80 - Forks: 6

Functional-Bus-Description-Language/go-fbdl
Functional Bus Description Language compiler front-end written in Go.
Language: Go - Size: 1.3 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 1

Functional-Bus-Description-Language/go-vfbdb
Versatile Functional Bus Description Language compiler back-end written in Go.
Language: VHDL - Size: 492 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 1

ZipCPU/autofpga
A utility for Composing FPGA designs from Peripherals
Language: C++ - Size: 2.42 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 170 - Forks: 19

alinja/alpus_wb
VHDL implementation of Pipelined Wishbone B4 interconnect
Language: VHDL - Size: 13.7 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

lxp32/lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Language: Assembly - Size: 3.4 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 59 - Forks: 13

ZipCPU/wbi2c
Wishbone controlled I2C controllers
Language: Verilog - Size: 759 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 44 - Forks: 10

rlee287/hardware-bus-infrastructure
A collection of formal properties for hardware buses, and cores using them.
Language: Verilog - Size: 78.1 KB - Last synced at: about 15 hours ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 0

ZipCPU/openarty
An Open Source configuration of the Arty platform
Language: Verilog - Size: 14.2 MB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 122 - Forks: 24

ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
Language: Verilog - Size: 256 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1,289 - Forks: 154

ZipCPU/wbuart32
A simple, basic, formally verified UART controller
Language: Verilog - Size: 1.19 MB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 266 - Forks: 46

cyber-murmel/nmigen-wishbone-examples
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
Language: Python - Size: 298 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

daniel-santos-7/leaf
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
Language: VHDL - Size: 660 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 3

jakubcabal/rmii-firewall-fpga
RMII Firewall FPGA
Language: VHDL - Size: 98.6 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 13 - Forks: 3

pbing/Wishbone
Check Wishbone B4 variants
Language: SystemVerilog - Size: 946 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

jakubcabal/uart-for-fpga
Simple UART controller for FPGA written in VHDL
Language: VHDL - Size: 97.7 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 65 - Forks: 23

ZipCPU/dbgbus
A collection of debugging busses developed and presented at zipcpu.com
Language: Verilog - Size: 324 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 23 - Forks: 3

ZipCPU/wbfmtx
A wishbone controlled FM transmitter hack
Language: Verilog - Size: 197 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 19 - Forks: 1

semahawk/icarium
Trying to implement a soft core SoC
Language: Verilog - Size: 559 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 0

ZipCPU/s6soc
CMod-S6 SoC
Language: Verilog - Size: 2.8 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 33 - Forks: 5

ZipCPU/xulalx25soc
A System on a Chip Implementation for the XuLA2-LX25 board
Language: Verilog - Size: 475 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 15 - Forks: 3

pbing/J1_WB
Forth CPU J1 in SystemVerilog and Wishbone interface
Language: SystemVerilog - Size: 3.13 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1

semahawk/wishbone
Trying to learn Wishbone by implementing few master/slave devices
Language: SystemVerilog - Size: 385 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 2
