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GitHub / ZipCPU / wb2axip
Bus bridges and other odds and ends
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwb2axip
Stars: 422
Forks: 94
Open Issues: 5
License: None
Language: Verilog
Repo Size: 8.97 MB
Dependencies:
0
Created: over 7 years ago
Updated: 3 months ago
Last pushed: 5 months ago
Last synced: 3 months ago
Topics: axi-bus, fpga, gplv3, wishbone, wishbone-bus, xilinx, xilinx-vivado
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