GitHub topics: wishbone

Repositories

PacoReinaCampo/MPSoC-MPI

Message Passing Interface for MPSoC

Language: SystemVerilog - Size: 20.2 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 3 - Forks: 1

PacoReinaCampo/MPSoC-MSI

Master Slave Interface for MPSoC

Language: SystemVerilog - Size: 21.9 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 2

ZipCPU/sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Language: Verilog - Size: 15.1 MB - Last synced at: 5 days ago - Pushed at: 4 months ago - Stars: 273 - Forks: 43

PacoReinaCampo/MPSoC-UART

Universal Asynchronous Receiver-Transmitter for MPSoC

Language: SystemVerilog - Size: 21.3 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 3

PacoReinaCampo/MPSoC-SPRAM

Single-Port RAM for Instruction & Data for MPSoC

Language: SystemVerilog - Size: 18.4 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 2

PacoReinaCampo/MPSoC-MPRAM

Multi-Port RAM for Instruction & Data for MPSoC

Language: SystemVerilog - Size: 20.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 4

PacoReinaCampo/MPSoC-GPIO

General Purpose Input Output for MPSoC

Language: SystemVerilog - Size: 20.4 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 4

PacoReinaCampo/MPSoC-DMA

Direct Access Memory for MPSoC

Language: SystemVerilog - Size: 23.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 12 - Forks: 6

PacoReinaCampo/MPSoC-DBG

Debugger on Chip for MPSoC

Language: SystemVerilog - Size: 27.9 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 5

ZipCPU/wb2axip

Bus bridges and other odds and ends

Language: Verilog - Size: 8.78 MB - Last synced at: 5 days ago - Pushed at: 13 days ago - Stars: 544 - Forks: 110

ZipCPU/wbscope

A wishbone controlled scope for FPGA's

Language: Verilog - Size: 758 KB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 80 - Forks: 6

pbing/ibex_wb

RISC-V Ibex core with Wishbone B4 interface

Language: C - Size: 1.09 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 15 - Forks: 4

ZipCPU/autofpga

A utility for Composing FPGA designs from Peripherals

Language: C++ - Size: 2.42 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 170 - Forks: 19

merledu/caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.

Language: Scala - Size: 820 KB - Last synced at: 5 days ago - Pushed at: about 1 month ago - Stars: 14 - Forks: 11

alinja/alpus_wb

VHDL implementation of Pipelined Wishbone B4 interconnect

Language: VHDL - Size: 13.7 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

lxp32/lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Language: Assembly - Size: 3.4 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 59 - Forks: 13

ZipCPU/openarty

An Open Source configuration of the Arty platform

Language: Verilog - Size: 14.2 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 122 - Forks: 24

ZipCPU/zipcpu

A small, light weight, RISC CPU soft core

Language: Verilog - Size: 256 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1,289 - Forks: 154

ZipCPU/wbuart32

A simple, basic, formally verified UART controller

Language: Verilog - Size: 1.19 MB - Last synced at: 9 months ago - Pushed at: about 1 year ago - Stars: 266 - Forks: 46

daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

Language: Verilog - Size: 29.3 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 5 - Forks: 2

BLangOS/VexRiscV_with_HW-GDB_Server

VexRiscV system with GDB-Server in Hardware

Language: VHDL - Size: 346 KB - Last synced at: 17 days ago - Pushed at: almost 2 years ago - Stars: 20 - Forks: 4

cyber-murmel/nmigen-wishbone-examples

A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91

Language: Python - Size: 298 KB - Last synced at: 12 months ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

ZipCPU/wbicapetwo

Wishbone to ICAPE interface conversion

Language: Verilog - Size: 177 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 7 - Forks: 1

lingbai-kong/computer-system

同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植

Language: Verilog - Size: 109 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 8 - Forks: 0

hotwolf/WbXbc

HDL components to build a customized Wishbone crossbar switch

Language: SystemVerilog - Size: 1.62 MB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 8 - Forks: 2

pbing/Wishbone_BSV

Wishbone/Bluespec Systemverilog Transactors

Language: Verilog - Size: 958 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

pbing/Wishbone

Check Wishbone B4 variants

Language: SystemVerilog - Size: 946 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

stnolting/wb_spi_bridge

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

Language: VHDL - Size: 128 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 19 - Forks: 0

jakubcabal/uart-for-fpga

Simple UART controller for FPGA written in VHDL

Language: VHDL - Size: 97.7 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 65 - Forks: 23

ZipCPU/dbgbus

A collection of debugging busses developed and presented at zipcpu.com

Language: Verilog - Size: 324 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 23 - Forks: 3

ZipCPU/wbfmtx

A wishbone controlled FM transmitter hack

Language: Verilog - Size: 197 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 19 - Forks: 1

semahawk/icarium

Trying to implement a soft core SoC

Language: Verilog - Size: 559 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 0

panda5mt/qf_wbfpga_pio

QuickLogic EOS S3:Cortex-M4 to FPGA Fabric via WISHBONE bus Sample Code with 8bit CAMERA-IF

Language: C - Size: 7.29 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 1

rschlaikjer/fpga-3-softcores

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

Language: Verilog - Size: 10 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 2

ZipCPU/s6soc

CMod-S6 SoC

Language: Verilog - Size: 2.8 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 33 - Forks: 5

pbing/J1_WB

Forth CPU J1 in SystemVerilog and Wishbone interface

Language: SystemVerilog - Size: 3.13 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1

semahawk/wishbone

Trying to learn Wishbone by implementing few master/slave devices

Language: SystemVerilog - Size: 385 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 2

In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.

Language: Verilog - Size: 61.5 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 0

EnricoRuggiano/stm32-watchdogs

Language: SystemVerilog - Size: 31.3 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

mickeyfying/PyWishUniquely

With this Repository One Can actually wish someone in a very unique programmers way and One Can Actually Also Choose to update the name and Illustrations that will be involved It is actually Lovely Because People will love your unique way of wishing and they will actually remember the way you wished them on their birthday

Language: Python - Size: 4.95 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 2

Related Keywords

wishbone 49 wishbone-bus 19 fpga 17 verilog 12 verilator 9 ahb3-lite 8 python 8 vhdl 5 fpga-soc 5 event-processing 4 microservices 4 microservice 4 event-driven 3 cpu 3 systemverilog 3 soft-core 3 risc-v 3 zipcpu 3 uart 3 verilog-hdl 3 softcore 2 hdl 2 risc-cpu 2 spi 2 queues 2 system-on-chip 2 azure 2 rabbitmq 2 verilog-components 2 messaging 2 gplv3 2 xilinx 2 amqp 2 debugging-tools 2 middleware 2 spi-interface 2 simulation 1 hardware-description-language 1 zmc 1 processordesign 1 highperformance 1 forth-cpu 1 cyc1000 1 quicklogic 1 controller 1 efpga 1 ghdl 1 uart-controller 1 bluespec-systemverilog 1 hack 1 xip 1 fm-transmitter 1 flash 1 fgpa 1 memory 1 uart-loopback 1 neorv32 1 stream-processing 1 microservice-framework 1 http-client 1 events 1 twitter 1 http-server 1 http 1 wishing 1 wishes 1 wayofwishing 1 unique 1 shivamsingh 1 pythonscripting 1 python3 1 programmersway 1 practicallyamazing 1 of 1 mickeycoding59 1 happy-birthday 1 watchdog 1 system-verilog 1 stm32 1 bluespec 1 clock-generator 1 uart-verilog 1 serialport 1 cross-compiler 1 arty 1 risc-processor 1 risc 1 assembly 1 assembler 1 soc 1 interconnect 1 bus 1 on-chip-network 1 chisel3 1 chisel-generator 1 caravan 1 bus-protocols 1 amba 1 c-plus-plus 1 riscv 1