Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: wishbone

Repositories

PacoReinaCampo/MPSoC-SPRAM

Single-Port RAM for Instruction & Data for MPSoC

Language: SystemVerilog - Size: 16.5 MB - Last synced: about 7 hours ago - Pushed: about 9 hours ago - Stars: 3 - Forks: 2

PacoReinaCampo/MPSoC-MSI

Master Slave Interface for MPSoC

Language: SystemVerilog - Size: 19.9 MB - Last synced: about 7 hours ago - Pushed: about 9 hours ago - Stars: 2 - Forks: 2

PacoReinaCampo/MPSoC-MPRAM

Multi-Port RAM for Instruction & Data for MPSoC

Language: SystemVerilog - Size: 18.9 MB - Last synced: about 7 hours ago - Pushed: about 9 hours ago - Stars: 3 - Forks: 4

PacoReinaCampo/MPSoC-MPI

Message Passing Interface for MPSoC

Language: SystemVerilog - Size: 18.6 MB - Last synced: about 7 hours ago - Pushed: about 9 hours ago - Stars: 3 - Forks: 1

PacoReinaCampo/MPSoC-DMA

Direct Access Memory for MPSoC

Language: SystemVerilog - Size: 19.9 MB - Last synced: about 7 hours ago - Pushed: about 9 hours ago - Stars: 12 - Forks: 6

PacoReinaCampo/MPSoC-DBG

Debugger on Chip for MPSoC

Language: SystemVerilog - Size: 26.1 MB - Last synced: about 7 hours ago - Pushed: about 9 hours ago - Stars: 1 - Forks: 5

ZipCPU/sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Language: Verilog - Size: 7.1 MB - Last synced: 16 days ago - Pushed: 16 days ago - Stars: 146 - Forks: 25

PacoReinaCampo/MPSoC-UART

Universal Asynchronous Receiver-Transmitter for MPSoC

Language: SystemVerilog - Size: 19.3 MB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 4 - Forks: 3

ZipCPU/zipcpu

A small, light weight, RISC CPU soft core

Language: Verilog - Size: 259 MB - Last synced: 17 days ago - Pushed: 17 days ago - Stars: 1,202 - Forks: 150

cyber-murmel/nmigen-wishbone-examples

A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91

Language: Python - Size: 298 KB - Last synced: about 1 month ago - Pushed: over 3 years ago - Stars: 2 - Forks: 0

PacoReinaCampo/MPSoC-GPIO

General Purpose Input Output for MPSoC

Language: SystemVerilog - Size: 17.8 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 3 - Forks: 4

ZipCPU/wb2axip

Bus bridges and other odds and ends

Language: Verilog - Size: 8.97 MB - Last synced: 3 months ago - Pushed: 5 months ago - Stars: 422 - Forks: 94

ZipCPU/wbscope

A wishbone controlled scope for FPGA's

Language: Verilog - Size: 758 KB - Last synced: 3 months ago - Pushed: 5 months ago - Stars: 68 - Forks: 6

ZipCPU/wbuart32

A simple, basic, formally verified UART controller

Language: Verilog - Size: 1.19 MB - Last synced: 3 months ago - Pushed: 4 months ago - Stars: 240 - Forks: 47

ZipCPU/autofpga

A utility for Composing FPGA designs from Peripherals

Language: C++ - Size: 2.09 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 153 - Forks: 17

ZipCPU/openarty

An Open Source configuration of the Arty platform

Language: Verilog - Size: 14.2 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 112 - Forks: 23

ZipCPU/wbicapetwo

Wishbone to ICAPE interface conversion

Language: Verilog - Size: 177 KB - Last synced: 8 months ago - Pushed: about 4 years ago - Stars: 7 - Forks: 1

daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

Language: Verilog - Size: 23.4 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

BLangOS/VexRiscV_with_HW-GDB_Server

VexRiscV system with GDB-Server in Hardware

Language: VHDL - Size: 346 KB - Last synced: 11 months ago - Pushed: over 2 years ago - Stars: 15 - Forks: 4

lingbai-kong/computer-system

同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植

Language: Verilog - Size: 109 MB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 8 - Forks: 0

merledu/caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.

Language: Scala - Size: 798 KB - Last synced: 3 months ago - Pushed: 9 months ago - Stars: 12 - Forks: 10

hotwolf/WbXbc

HDL components to build a customized Wishbone crossbar switch

Language: SystemVerilog - Size: 1.62 MB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 8 - Forks: 2

pbing/Wishbone_BSV

Wishbone/Bluespec Systemverilog Transactors

Language: Verilog - Size: 958 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

pbing/Wishbone

Check Wishbone B4 variants

Language: SystemVerilog - Size: 946 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

stnolting/wb_spi_bridge

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

Language: VHDL - Size: 128 KB - Last synced: over 1 year ago - Pushed: over 2 years ago - Stars: 19 - Forks: 0

pbing/ibex_wb

RISC-V Ibex core with Wishbone B4 interface

Language: HTML - Size: 858 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 11 - Forks: 3

jakubcabal/uart-for-fpga

Simple UART controller for FPGA written in VHDL

Language: VHDL - Size: 97.7 KB - Last synced: over 1 year ago - Pushed: almost 3 years ago - Stars: 65 - Forks: 23

ZipCPU/dbgbus

A collection of debugging busses developed and presented at zipcpu.com

Language: Verilog - Size: 324 KB - Last synced: over 1 year ago - Pushed: over 1 year ago - Stars: 23 - Forks: 3

lxp32/lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Language: Assembly - Size: 2.92 MB - Last synced: over 1 year ago - Pushed: almost 2 years ago - Stars: 49 - Forks: 11

ZipCPU/wbfmtx

A wishbone controlled FM transmitter hack

Language: Verilog - Size: 197 KB - Last synced: over 1 year ago - Pushed: over 4 years ago - Stars: 19 - Forks: 1

semahawk/icarium

Trying to implement a soft core SoC

Language: Verilog - Size: 559 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 4 - Forks: 0

panda5mt/qf_wbfpga_pio

QuickLogic EOS S3:Cortex-M4 to FPGA Fabric via WISHBONE bus Sample Code with 8bit CAMERA-IF

Language: C - Size: 7.29 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 4 - Forks: 1

rschlaikjer/fpga-3-softcores

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

Language: Verilog - Size: 10 MB - Last synced: over 1 year ago - Pushed: almost 4 years ago - Stars: 4 - Forks: 2

ZipCPU/s6soc

CMod-S6 SoC

Language: Verilog - Size: 2.8 MB - Last synced: over 1 year ago - Pushed: over 6 years ago - Stars: 33 - Forks: 5

pbing/J1_WB

Forth CPU J1 in SystemVerilog and Wishbone interface

Language: SystemVerilog - Size: 3.13 MB - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 1 - Forks: 1

semahawk/wishbone

Trying to learn Wishbone by implementing few master/slave devices

Language: SystemVerilog - Size: 385 KB - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 3 - Forks: 2

In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.

Language: Verilog - Size: 61.5 KB - Last synced: 12 months ago - Pushed: almost 3 years ago - Stars: 4 - Forks: 0

EnricoRuggiano/stm32-watchdogs

Language: SystemVerilog - Size: 31.3 KB - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 1 - Forks: 0

mickeyfying/PyWishUniquely

With this Repository One Can actually wish someone in a very unique programmers way and One Can Actually Also Choose to update the name and Illustrations that will be involved It is actually Lovely Because People will love your unique way of wishing and they will actually remember the way you wished them on their birthday

Language: Python - Size: 4.95 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 1 - Forks: 2

Related Keywords

wishbone 48 wishbone-bus 18 fpga 16 verilog 12 verilator 9 python 8 ahb3-lite 8 event-processing 4 microservices 4 vhdl 4 microservice 4 fpga-soc 4 verilog-hdl 3 risc-v 3 event-driven 3 systemverilog 3 uart 3 cpu 3 soft-core 3 zipcpu 3 softcore 2 azure 2 rabbitmq 2 queues 2 spi 2 middleware 2 hdl 2 spi-interface 2 verilog-components 2 messaging 2 risc-cpu 2 debugging-tools 2 xilinx 2 gplv3 2 amqp 2 highperformance 1 cyc1000 1 processordesign 1 forth-cpu 1 quicklogic 1 efpga 1 system-on-chip 1 zmc 1 hardware-description-language 1 hack 1 fm-transmitter 1 risc-processor 1 risc 1 assembly 1 assembler 1 fgpa 1 uart-loopback 1 uart-controller 1 simulation 1 ghdl 1 stream-processing 1 microservice-framework 1 http-client 1 events 1 twitter 1 http-server 1 http 1 wishing 1 wishes 1 wayofwishing 1 unique 1 shivamsingh 1 pythonscripting 1 python3 1 programmersway 1 practicallyamazing 1 of 1 mickeycoding59 1 happy-birthday 1 watchdog 1 system-verilog 1 stm32 1 gdbserver 1 c-language 1 wishbone-master 1 verilog-rtl-model 1 verilog-project 1 verilog-code 1 testbench 1 spi-slave 1 spi-protocol 1 spi-master 1 rtl 1 clock-generator 1 iprog-command 1 arty 1 c-plus-plus 1 uart-verilog 1 serialport 1 xilinx-vivado 1 axi-bus 1 nmigen-soc 1 nmigen 1 cross-compiler 1 sdio 1