GitHub topics: ghdl

Repositories

stnolting/neorv32-riscof

✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

Language: Python - Size: 15.6 MB - Last synced at: about 13 hours ago - Pushed at: about 14 hours ago - Stars: 33 - Forks: 8

stnolting/neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Language: VHDL - Size: 846 KB - Last synced at: about 13 hours ago - Pushed at: about 14 hours ago - Stars: 75 - Forks: 24

stnolting/neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Language: VHDL - Size: 312 KB - Last synced at: about 13 hours ago - Pushed at: about 14 hours ago - Stars: 83 - Forks: 19

Cheetos19/EDA

Exploratory Data Analysis

Language: Jupyter Notebook - Size: 26.5 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

ghdl/ghdl

VHDL 2008/93/87 simulator

Language: VHDL - Size: 78.8 MB - Last synced at: 6 days ago - Pushed at: 7 days ago - Stars: 2,551 - Forks: 382

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.09 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 682 - Forks: 200

nobodywasishere/upduino-projects

Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

Language: VHDL - Size: 14.9 MB - Last synced at: 6 days ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 2

PyFPGA/pyfpga

A Python package to use FPGA development tools programmatically.

Language: Python - Size: 7.15 MB - Last synced at: 15 days ago - Pushed at: about 2 months ago - Stars: 130 - Forks: 15

ElecGeek/PulsesGene

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

Language: VHDL - Size: 180 KB - Last synced at: 29 days ago - Pushed at: 29 days ago - Stars: 0 - Forks: 0

miree/gvi

GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.

Language: C++ - Size: 239 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 11 - Forks: 1

BDSM-hardware/lock_handler

Manages multi points bondage locks, for self or collective bondage.

Language: PostScript - Size: 2.85 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 3 - Forks: 0

tmeissner/libvhdl

Library of reusable VHDL components

Language: VHDL - Size: 263 KB - Last synced at: 6 days ago - Pushed at: about 1 year ago - Stars: 28 - Forks: 5

SethGower/dotfiles

The configuration files for my linux setup on my laptop and desktop.

Language: Lua - Size: 80 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 4 - Forks: 0

tmeissner/psl_with_ghdl

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

Language: VHDL - Size: 92.8 KB - Last synced at: 6 days ago - Pushed at: 3 months ago - Stars: 66 - Forks: 5

Paebbels/JSON-for-VHDL

A JSON library implemented in VHDL.

Language: VHDL - Size: 138 KB - Last synced at: 26 days ago - Pushed at: over 2 years ago - Stars: 78 - Forks: 17

PyFPGA/HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Language: Python - Size: 5.15 MB - Last synced at: 7 days ago - Pushed at: 2 months ago - Stars: 24 - Forks: 2

wyvernSemi/mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Language: VHDL - Size: 2.71 MB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 22 - Forks: 3

antsiri/Elaborato_di_Architettura_dei_Sistemi_Digitali

Elaborato ADSi - Proff. Nicola Mazzocca - Alessandra De Benedictis

Language: VHDL - Size: 106 MB - Last synced at: 7 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

ghdl/docker

Scripts to build and use docker images including GHDL

Language: Shell - Size: 250 KB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 42 - Forks: 11

PyFPGA/containers

Containers for FOSS tools

Language: Shell - Size: 31.3 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

edaa-org/pyEDAA.ToolSetup

Language: Python - Size: 2.84 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 5 - Forks: 0

tmeissner/gatemate_experiments

Experiments with Cologne Chip's GateMate FPGA architecture

Language: VHDL - Size: 114 KB - Last synced at: 6 days ago - Pushed at: over 1 year ago - Stars: 15 - Forks: 1

SalvatoreBarone/CNN-VHDL

A library of VHDL components for Neural Networks

Language: C++ - Size: 32.8 MB - Last synced at: 22 days ago - Pushed at: over 3 years ago - Stars: 17 - Forks: 3

JochiSt/icebreaker-VHDL

Some examples using VHDL in combination with the icebreaker board

Language: Makefile - Size: 14.6 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

tmeissner/formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

Language: VHDL - Size: 205 KB - Last synced at: 6 days ago - Pushed at: about 1 year ago - Stars: 41 - Forks: 7

umarcor/SIEAV

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

Language: VHDL - Size: 9.1 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 13 - Forks: 6

chuckb/ghdl-interactive-sim

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

Language: Python - Size: 252 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 9 - Forks: 3

suoto/hdl_checker

Repurposing existing HDL tools to help writing better code

Language: Python - Size: 1.05 MB - Last synced at: 6 months ago - Pushed at: 11 months ago - Stars: 192 - Forks: 22

AasmundN/rsa-hw-accelerator

Hardware accelerator for RSA encryption and decryption written in VHDL.

Language: VHDL - Size: 335 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 3 - Forks: 0

pat-pgt/MultiFrequenciesDetector

Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.

Language: VHDL - Size: 271 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

NikLeberg/vhpi_jtag

Connect to your GHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> vhpi_jtag <-VHPI-> GHDL

Language: C - Size: 37.1 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 7 - Forks: 1

ArbnorSh/RV-PipelineCore

RISC-V processor in compliance with RV32IMZicsr

Language: Verilog - Size: 1.82 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0

tmeissner/cryptocores

cryptography ip-cores in vhdl / verilog

Language: VHDL - Size: 238 KB - Last synced at: 6 days ago - Pushed at: about 4 years ago - Stars: 40 - Forks: 10

dominiksalvet/vhdl-collection

Collection of generic VHDL modules

Language: VHDL - Size: 306 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 8 - Forks: 5

dominiksalvet/risc63

Custom 64-bit pipelined RISC processor

Language: VHDL - Size: 421 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 13 - Forks: 1

Unike267/Practices

This repo contains the work developed in the SIEAV Master practices 🎓✏️📚

Language: VHDL - Size: 203 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

duclos-cavalcanti/templates

A meta repo with numerous different templates or boilerplate projects for several languages and technologies.

Language: Python - Size: 572 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

S0obi/GHDLDocumentation

Documentation for GHDL

Size: 1.95 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

guillaumebour/ying

Ying is a microcontroller based on a 16 bits RISC microprocessor with a 5-stage pipeline.

Language: VHDL - Size: 71.3 KB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

machitgarha/parvaj

Easy and fast VHDL simulation tool, integrating GHDL and GTKWave

Language: PHP - Size: 241 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 11 - Forks: 1

mnemocron/my-discrete-fpga

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

Language: VHDL - Size: 9.57 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

Kazhuu/vhdl-examples

VHDL examples for a different kind of topics

Language: VHDL - Size: 79.1 KB - Last synced at: about 1 month ago - Pushed at: almost 5 years ago - Stars: 4 - Forks: 1

rohankalbag/multicycle-risc Fork of IITB-RISC-2022/Multicycle_RISC

Course Project - Microprocessors - Spring Semester 2022 - Indian Institute of Technology Bombay

Language: VHDL - Size: 8.85 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

hargorin/udp_communication

UDP/IP communication between FPGA and PC

Language: VHDL - Size: 83.8 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

onegentig/VUT-FIT-IVH2023-projekt 📦

Projekt (animace na maticovém displeji) z předmětu Seminář VHDL (IVH), čtvrtý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Language: VHDL - Size: 420 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

marph91/icestick-remote

Remote control in VHDL, which fits on a Lattice icestick.

Language: VHDL - Size: 91.8 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 0

MatthieuMichon/boiler-plate-ghdl-osvvm

Language: VHDL - Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

MatthieuMichon/simfifo

FIFO functional model in VHDL-2008

Language: VHDL - Size: 8.79 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

jakubcabal/spi-fpga

SPI master and SPI slave for FPGA written in VHDL

Language: VHDL - Size: 2.78 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 145 - Forks: 36

qnighy/ghdl-hello

GHDL Sample Program & Makefile

Language: VHDL - Size: 117 KB - Last synced at: 7 months ago - Pushed at: over 10 years ago - Stars: 2 - Forks: 0

167rgc911/puart

Pseudo UART allowing to connect via pseudoterminal to GHDL simulated IP core

Language: VHDL - Size: 544 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

dbhi/vboard

Virtual development board for HDL design

Language: VHDL - Size: 383 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 33 - Forks: 5

VXAPPS/cmake-ghdl-compiler

GHDL Compiler Definition for CMake

Language: CMake - Size: 32.2 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

asl0007/DSD-VHDL-

PROGRAMS OF VHDL

Language: VHDL - Size: 2.26 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

PyFPGA/openflow

A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.

Language: Python - Size: 24.4 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 1

JulyWitch/vhdl_ghdl_examples

Simple VHDL examples using ghdl as compiler and wave generating

Language: VHDL - Size: 396 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 9 - Forks: 0

rohankalbag/superscalar-risc Fork of aweditya/superscalar

Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: VHDL - Size: 6.61 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Related Keywords

ghdl 77 vhdl 55 fpga 20 yosys 18 verilog 12 gtkwave 12 hardware 9 vivado 9 simulation 8 icestorm 7 verilator 7 xilinx 7 ghdl-yosys-plugin 7 vunit 5 modelsim 5 nextpnr 5 vhdl-code 5 synthesis 4 systemverilog 4 neorv32 4 python 4 quartus 4 formal-verification 4 docker 4 questasim 4 prjtrellis 4 tcl 3 cosimulation 3 ise 3 psl 3 fifo 3 vim 3 vhdl-examples 3 cocotb 3 testbench 3 makefile 3 processor 3 risc-v 3 lattice 3 verification 3 simulator 2 libero 2 testbenches 2 actions 2 vivado-simulator 2 symbiyosys 2 xilinx-fpga 2 cpu 2 osvvm 2 assertions 2 c 2 cosim 2 vpi 2 octave 2 yosys-slang 2 isa 2 hdl 2 eda 2 ice40 2 icestick 2 risc 2 rtl 2 soc 2 vscode 2 icarus-verilog 2 riviera-pro 2 uart 2 vhdl-testbench 2 controller 2 openocd 2 cyc1000 2 digital-design 1 vim-hdl 1 hdlcc 1 examples 1 jenkins-swarm 1 finite-state-machine 1 microprocessor 1 multicycle-risc 1 ip-communication 1 udp 1 udp-communication 1 fitkit 1 led-matrix 1 led-matrix-animation 1 matrix-display 1 university-project 1 vhdl-coursework 1 vhdl93 1 jenkins 1 java 1 haskell 1 gradle 1 golang 1 go 1 dockerfile 1 cpp 1 boilerplate-template 1 boilerplate 1 sieav 1