Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: ghdl

SethGower/dotfiles

The configuration files for my linux setup on my laptop and desktop.

Language: Shell - Size: 79.8 MB - Last synced: about 21 hours ago - Pushed: about 22 hours ago - Stars: 3 - Forks: 0

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1010 KB - Last synced: about 11 hours ago - Pushed: 1 day ago - Stars: 596 - Forks: 180

stnolting/neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

Language: Python - Size: 15.3 MB - Last synced: 2 days ago - Pushed: 3 days ago - Stars: 24 - Forks: 5

duclos-cavalcanti/templates

A meta repo with numerous different templates or boilerplate projects for several languages and technologies.

Language: Python - Size: 572 KB - Last synced: 3 days ago - Pushed: 3 days ago - Stars: 0 - Forks: 0

umarcor/SIEAV

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

Language: VHDL - Size: 9.14 MB - Last synced: 11 days ago - Pushed: 12 days ago - Stars: 10 - Forks: 6

stnolting/neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Language: Verilog - Size: 176 KB - Last synced: 17 days ago - Pushed: 20 days ago - Stars: 39 - Forks: 9

stnolting/neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Language: VHDL - Size: 644 KB - Last synced: 17 days ago - Pushed: 20 days ago - Stars: 52 - Forks: 15

S0obi/GHDLDocumentation

Documentation for GHDL

Size: 1.95 KB - Last synced: 21 days ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

guillaumebour/ying

Ying is a microcontroller based on a 16 bits RISC microprocessor with a 5-stage pipeline.

Language: VHDL - Size: 71.3 KB - Last synced: 25 days ago - Pushed: almost 6 years ago - Stars: 1 - Forks: 0

machitgarha/parvaj

Easy and fast VHDL simulation tool, integrating GHDL and GTKWave

Language: PHP - Size: 241 KB - Last synced: 20 days ago - Pushed: 3 months ago - Stars: 11 - Forks: 1

mnemocron/my-discrete-fpga

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

Language: VHDL - Size: 9.57 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 2 - Forks: 0

ghdl/ghdl

VHDL 2008/93/87 simulator

Language: VHDL - Size: 80.6 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 2,194 - Forks: 343

Kazhuu/vhdl-examples

VHDL examples for a different kind of topics

Language: VHDL - Size: 79.1 KB - Last synced: 17 days ago - Pushed: almost 4 years ago - Stars: 4 - Forks: 1

rohankalbag/multicycle-risc Fork of IITB-RISC-2022/Multicycle_RISC

Course Project - Microprocessors - Spring Semester 2022 - Indian Institute of Technology Bombay

Language: VHDL - Size: 8.85 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

hargorin/udp_communication

UDP/IP communication between FPGA and PC

Language: VHDL - Size: 83.8 MB - Last synced: 2 months ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

tmeissner/formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

Language: VHDL - Size: 205 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 41 - Forks: 7

SalvatoreBarone/CNN-VHDL

A library of VHDL components for Neural Networks

Language: C++ - Size: 32.8 MB - Last synced: 26 days ago - Pushed: over 2 years ago - Stars: 13 - Forks: 2

tmeissner/libvhdl

Library of reusable VHDL components

Language: VHDL - Size: 263 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 24 - Forks: 3

suoto/hdl_checker

Repurposing existing HDL tools to help writing better code

Language: Python - Size: 1.05 MB - Last synced: 3 months ago - Pushed: 5 months ago - Stars: 179 - Forks: 20

ElecGeek/PulsesGene

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

Language: PostScript - Size: 163 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

pat-pgt/MultiFrequenciesDetector

Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.

Language: VHDL - Size: 121 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0

onegentig/VUT-FIT-IVH2023-projekt 📦

Projekt (animace na maticovém displeji) z předmětu Seminář VHDL (IVH), čtvrtý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Language: VHDL - Size: 420 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

marph91/icestick-remote

Remote control in VHDL, which fits on a Lattice icestick.

Language: VHDL - Size: 91.8 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 8 - Forks: 0

MatthieuMichon/boiler-plate-ghdl-osvvm

Language: VHDL - Size: 5.86 KB - Last synced: 5 months ago - Pushed: 11 months ago - Stars: 0 - Forks: 0

MatthieuMichon/simfifo

FIFO functional model in VHDL-2008

Language: VHDL - Size: 8.79 KB - Last synced: 5 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

ghdl/docker

Scripts to build and use docker images including GHDL

Language: Shell - Size: 245 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 34 - Forks: 11

jakubcabal/spi-fpga

SPI master and SPI slave for FPGA written in VHDL

Language: VHDL - Size: 2.78 MB - Last synced: 6 months ago - Pushed: about 3 years ago - Stars: 145 - Forks: 36

miree/gvi

GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.

Language: C++ - Size: 146 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 5 - Forks: 0

PyFPGA/pyfpga

A Python package to use FPGA development tools programmatically.

Language: Python - Size: 4.25 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 61 - Forks: 6

JochiSt/icebreaker-VHDL

Some examples using VHDL in combination with the icebreaker board

Language: Makefile - Size: 14.6 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

167rgc911/puart

Pseudo UART allowing to connect via pseudoterminal to GHDL simulated IP core

Language: VHDL - Size: 544 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 1 - Forks: 0

dbhi/vboard

Virtual development board for HDL design

Language: VHDL - Size: 383 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 33 - Forks: 5

tmeissner/psl_with_ghdl

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

Language: VHDL - Size: 165 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 53 - Forks: 3

asl0007/DSD-VHDL-

PROGRAMS OF VHDL

Language: VHDL - Size: 2.26 MB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 1 - Forks: 0

PyFPGA/openflow

A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.

Language: Python - Size: 24.4 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 3 - Forks: 1

Paebbels/JSON-for-VHDL

A JSON library implemented in VHDL.

Language: VHDL - Size: 138 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 67 - Forks: 13

JulyWitch/vhdl_ghdl_examples

Simple VHDL examples using ghdl as compiler and wave generating

Language: VHDL - Size: 396 KB - Last synced: 12 months ago - Pushed: almost 2 years ago - Stars: 9 - Forks: 0

tmeissner/gatemate_experiments

Experiments with Cologne Chip's GateMate FPGA architecture

Language: VHDL - Size: 111 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 7 - Forks: 0

chuckb/ghdl-interactive-sim

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

Language: Python - Size: 252 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 3 - Forks: 1

rohankalbag/superscalar-risc Fork of aweditya/superscalar

Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: VHDL - Size: 6.61 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

167rgc911/hdl_study

mostly simple VHDL stuff

Size: 110 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

YoussefRaafatNasry/vhdl-docker-template

Template for creating VHDL project using docker

Language: VHDL - Size: 2.93 KB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 5 - Forks: 1

jakubcabal/uart-for-fpga

Simple UART controller for FPGA written in VHDL

Language: VHDL - Size: 97.7 KB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 65 - Forks: 23

johannesbonk/vscode-ghdl-interface

A tool to invoke ghdl/gtkwave functions, including error highlighting

Language: JavaScript - Size: 16.1 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 4 - Forks: 5

marph91/icestick-uart

Lightweight UART implementation in VHDL for the lattice icestick

Language: VHDL - Size: 22.5 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 2 - Forks: 0

tmeissner/cryptocores

cryptography ip-cores in vhdl / verilog

Language: VHDL - Size: 238 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 37 - Forks: 9

rodrigomelo9/verifying-foss-hdl-synthesizers

a project to check the FOSS synthesizers against vendors EDA tools

Language: Makefile - Size: 81.1 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 12 - Forks: 2

dbhi/containers

Containerized open and free development tools for Dynamic Binary Hardware Injection (DBHI)

Language: Dockerfile - Size: 123 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 4 - Forks: 1

cajt/ghdlsynth-testcase-loa

A "test" for GHDL Synthesis. Including logs for https://github.com/tgingold/ghdlsynth-beta/issues/87 .

Language: VHDL - Size: 36.1 KB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 1 - Forks: 0

nobodywasishere/upduino-projects

Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

Language: VHDL - Size: 14.9 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 6 - Forks: 1

rafaelnp/fpga_dev_docker

Docker image for fpga development

Language: Dockerfile - Size: 9.77 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 2 - Forks: 0

PLC2/Solution-StopWatch

Professional VHDL Class Solution - StopWatch

Language: VHDL - Size: 279 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 4 - Forks: 2

PyFPGA/poc

Proofs of concept about FPGA EDA tools.

Language: Shell - Size: 37.1 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 2 - Forks: 0

lrsb/digitallogicdesign-vhdl-2019

A VHDL implementation of a Manhattan distance calculator

Language: VHDL - Size: 589 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 0

eine/ghdl-packaging

Sources for package management systems to build GHDL

Language: Shell - Size: 61.5 KB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 1 - Forks: 7

PyFPGA/symbiflow_cli

A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project

Language: Python - Size: 470 KB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 0 - Forks: 0

baptistepetit/cordic

A Naive CORDIC implementation

Language: VHDL - Size: 150 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 1 - Forks: 0

RubioHaro/VHDL

Language: VHDL - Size: 12 MB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 1 - Forks: 0

tivaliy/ghdl-jenkins-swarm-slave

Docker-based Jenkins swarm slave client with GHDL software

Language: Shell - Size: 3.91 KB - Last synced: about 1 year ago - Pushed: about 7 years ago - Stars: 0 - Forks: 0

syfluqs/hdl_scratchpad

VHDL scratchpad

Language: VHDL - Size: 4.49 MB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 0 - Forks: 1

doppioandante/vivado_tools

Command line utilities for GHDL+vivado project management and simulation

Language: Shell - Size: 5.86 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 0 - Forks: 0

qnighy/ghdl-hello

GHDL Sample Program & Makefile

Language: VHDL - Size: 117 KB - Last synced: about 1 year ago - Pushed: over 9 years ago - Stars: 2 - Forks: 0

eggsactly/VHDL-FIFO

FIFO implemented in VHDL.

Language: VHDL - Size: 10.7 KB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 0 - Forks: 0