CTipton27/FPGA_Pong

Language: VHDL - Size: 21.5 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0

mikeroyal/VHDL-Guide

VHDL Guide

Language: VHDL - Size: 135 KB - Last synced at: 4 days ago - Pushed at: over 3 years ago - Stars: 64 - Forks: 8

bryan-hoang/elec-271-digital-systems-labs 📦

VHDL Code for Labs done in a 2nd year engineering Digital Systems course (ELEC 271) at Queen's University.

Language: VHDL - Size: 10.7 KB - Last synced at: 2 days ago - Pushed at: 7 months ago - Stars: 3 - Forks: 1

Alexandra07e/AC-secret

Arhitectura Calculatoarelor (VERILOG) - probleme rezolvate de mine (edaplayground flood)

Size: 1.95 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

npwitk/EES270-Digital-Circuits-Laboratory-VHDL

A repository of VHDL code from the EES270 Digital Circuits Laboratory course at SIIT, including implementations and simulations for various digital circuits designed during lab sessions.

Language: VHDL - Size: 14.6 KB - Last synced at: 17 days ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

ynarter/EE102

Labs and project for the EE102 Introduction to Digital Circuit Design course.

Language: HTML - Size: 11.8 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

GeorgesCoding/Traffic-Lights

Traffic light system for a four way intersection simulated using a Moore state machine and displayed on a FPGA

Language: VHDL - Size: 4.81 MB - Last synced at: 4 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

rgeleon/VHDL_samples

Vhdl coursework

Language: VHDL - Size: 620 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

ITSUREN/ComputerArchitecture

🏛️ [RUSHED🏃‍♀️] A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for Academics.

Language: VHDL - Size: 707 KB - Last synced at: 4 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

rockyhuiop/CENG3430-AirFighter

2 Players Airplane Battle Arcade game on Zynq, using FPGA Zedboard to output VGA signal to display on 1024*600 monitor

Language: VHDL - Size: 269 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Marco-Winzker/FPGA-FIR-Filter

Lecture about FIR filter on an FPGA

Language: VHDL - Size: 465 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 12 - Forks: 6

aliemo/aut-ce-fpga-homeworks 📦

Programmable Systems Design Course Teaching Assistant at Tehran Polytechnic

Language: VHDL - Size: 2.67 MB - Last synced at: about 1 year ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

dylanrichards/EGR480

EGR 480 - Digital Integrated Circuit Design and FPGAs

Language: VHDL - Size: 10.7 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

jkleiber/ECE4613 📦

Computer Architecture VHDL code

Language: VHDL - Size: 302 KB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

urbanij/DDFS

Direct digital frequency synthesizer in Verilog and VHDL.

Language: VHDL - Size: 9.56 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 2

pronoym99/PN-Sequence-Generator

This is a simulation based VHDL code developed in Xilinx to demonstrate a 4-bit PN sequence generator.

Language: C++ - Size: 2.38 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

francescospangaro/ProgettoRL

Prova finale di Reti Logiche A.A. 2022/2023

Language: VHDL - Size: 5.33 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 1

onegentig/VUT-FIT-INP2022-projekt1 📦

První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Language: VHDL - Size: 2.42 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

onegentig/VUT-FIT-INC2022-projekt 📦

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

Language: VHDL - Size: 255 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

onegentig/VUT-FIT-IVH2023-projekt 📦

Projekt (animace na maticovém displeji) z předmětu Seminář VHDL (IVH), čtvrtý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Language: VHDL - Size: 420 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

html-3/sd-ula

O objetivo do deste projeto foi modelar, programar e testar uma Unidade Lógica e Aritmética, de quatro operações, usando os conhecimentos adquiridos em Circuitos Lógicos e aplicados nas aulas práticas no laboratório de Sistemas Digitais.

Language: VHDL - Size: 207 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

shahjui2000/Push-Button-Door-VHDL-

Simulation of a push button door lock with a variable password

Size: 160 KB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1

aliansgp/VHDL_Multipliers

Different Multipliers code in VHDL and Comparison

Language: C - Size: 1.35 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Chrisdeleon91/Altera-DE1-VGA-Interface

Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.

Language: VHDL - Size: 8.2 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

josefdc/Laboratorio-Fundamentos-De-Electronica

Este repositorio es el hogar del curso de Fundamentos de Electrónica de la Universidad Tecnológica de Pereira. Aquí, los estudiantes y profesores pueden colaborar en el desarrollo y mejora continua del curso, compartiendo materiales didácticos, ejercicios prácticos, proyectos y más.

Language: VHDL - Size: 222 KB - Last synced at: 21 days ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 2

blackprince001/blocks-of-vhdl

Repository for everything VHDL Course - Digital Systems Design II (Prof K. O. Boateng)

Language: VHDL - Size: 734 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

hk-117/VHDL

Some example of vhdl code, using ghdl and gtkwave.

Language: VHDL - Size: 30.3 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

yash2410/FIRFilter

A design of FIR filter using VHDL

Language: VHDL - Size: 50.8 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

yash2410/Traffic-Light-Controller-

TLC designed vhdl which changes the green light time depending on the traffic in that specfic lane

Language: VHDL - Size: 7.64 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

gholomia/Fusion

Crawling deep into the world of hardware description language, VHDL. My coursework for the digital design of computer systems course by Dr. M. Saheb Zamani.

Language: JavaScript - Size: 90.6 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 5 - Forks: 0

JungleEngine/Project_ARCH_2

Simplified implementation of MIPS pipelined processor

Language: VHDL - Size: 272 KB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

mahdihaghverdi/cpu

Simple single cycle CPU written in VHDL

Language: VHDL - Size: 23.2 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 1

nedaraad/MSc-Synthesis

Homework and Project for Master Course (Synthesis of Digital Systems)

Language: VHDL - Size: 1.14 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

vaniseth/Computer-Organisation-and-Architecture-Lab

Implementing circuits through VHDL

Language: HTML - Size: 11.1 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Ryuzaki101/Programmable-logic-components

Xilinix VHDL Projects

Language: C - Size: 3.49 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

haideraheem/Programming-FPGA-Basys3-with-VHDL

This repository contains beginner to intermediate level of codes for VHDL and Basys 3.

Size: 6.53 MB - Last synced at: 6 months ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 1

jhenals/VHDL-Code---Circuito-Sequenziale

Secondo Progetto di Elettronico Digitale AA2022-2023

Size: 4.33 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

jhenals/VHDL-Code---Carry-Select-32bit

Progetto di Elettronica Digitale AA 2022-2023

Size: 4.67 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

LukeKan/fpga-manhattan-distance

FPGA design project for the course "Reti Logiche" of Politecnico di Milano, a.y. 2018/2019

Language: VHDL - Size: 293 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

eimon96/VHDL

Language: VHDL - Size: 342 KB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

torland-klev/INF3430-Projects 📦

Language: VHDL - Size: 51 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

mmahdim/FPGA-DotMatrix

FPGA Dot Matrix Display with VHDL

Language: HTML - Size: 623 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 0

JoaoPNVieira/LSD

Laboratório de Sistemas Digitais - Universidade de Aveiro

Language: VHDL - Size: 112 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

manish-9245/VHDL-Programs

This repository contains VHDL files of different Digital Designs.

Language: VHDL - Size: 4.49 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 0

fennecfox38/VHDLtraining

Sample VHDL Example

Language: VHDL - Size: 64.5 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

De-Bola/ias0600_vhdl

Language: HTML - Size: 35.3 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

aut-ce/CE242-PDS

Programmable Digital Systems Design Course Materials

Language: VHDL - Size: 2.73 MB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 1

chkrr00k/hex-controller

Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board

Language: VHDL - Size: 6.84 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

chkrr00k/sram-controller

A simple sram controller and test for the altera DE1 FPGA board

Language: VHDL - Size: 15.6 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 2