GitHub topics: altera-de1
EngineerMichael/ModelSim-Altera-Project-Electronics-
⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.
Size: 25.4 KB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 0
anchaides/docker-arm-gnuabihf-de1-soc
Helps with Cross compilation for arm-gnueabihf-gcc linux compilation for the HPS found in cyclone V subsystems on DE1-SOC boards.
Language: Dockerfile - Size: 14.6 KB - Last synced at: 11 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
pedro-javierf/AlteraDE1pinfiles
Pin file in .qsf format for Altera DE1 FPGA
Language: Tcl - Size: 5.46 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
inmerso/funky_appliance
Kitchen-timer on Altera DE1 FPGA development kit - VHDL
Language: VHDL - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Chrisdeleon91/Altera-DE1-VGA-Interface
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
Language: VHDL - Size: 8.2 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
jxwleong/altera-de1-processor
Synthesize a general purpose microprocessor (GPM) using verilog hdl code on Altera DE1 development board. The processor was used to find the greatest common divisor (GCD) between two integers.
Language: Verilog - Size: 9.14 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1
Nativu5/DE1-SoC-MyPlayer
A Music Player on DE1-SoC Board.
Language: C - Size: 1.77 MB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
kianwasabi/Sync_Lights_Altera-DE1-Board
Altera-DE1-Board: IIR&FIR-Filter,VGA & Audio synch. Light
Language: VHDL - Size: 8.46 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
jxwleong/altera-de1-traffic-light-controller
Using finite state machine (FSM) approach to design a traffic light controller on Altera DE1 development board.
Language: Verilog - Size: 18.8 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 1
ismailfaruk/ECSE324--Computer-Organization
Academic projects created using Assembly, in the Intel FPGA Monitor Program, for the laboratory work done while attending the McGill Course ECSE 324 Computer Organization
Language: Assembly - Size: 8.95 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 3
Cesarsk/the_snake_game
The Snake Game Made in VHDL for Altera DE1 using Quartus V.13
Language: VHDL - Size: 30.7 MB - Last synced at: 12 days ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0
chkrr00k/hex-controller
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
Language: VHDL - Size: 6.84 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0
chkrr00k/sram-controller
A simple sram controller and test for the altera DE1 FPGA board
Language: VHDL - Size: 15.6 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 2