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GitHub topics: altera-quartus

ab-ff/Multi-Bit-Comparator

Variations of a multi-bit generalized comparator for different area and timing.

Size: 1000 Bytes - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

SKpro-glitch/Multi-Bit-Comparator

Variations of a multi-bit generalized magnitude comparator for different area and timing.

Language: Verilog - Size: 33.2 KB - Last synced at: 28 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

EngineerMichael/ModelSim-Altera-Project-Electronics-

⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.

Size: 25.4 KB - Last synced at: about 2 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 0

Charlie-Ramirez-Animation-Studios-de-MX/VHDL-Basicos

Programas Basicos en Lenguaje VHDL de Diseño Logico y Diseño de Circuitos Digitales para Uso y simulacion con QuartusII y los FPGA Cyclone III de Altera (Compilados y compatibles con la FPGA EP3C16F484C6N) Para Practica en la Licenciatura de Ingenieria Electrica Electronica e Ingenieria en Computación Bajo Licencia MIT

Language: VHDL - Size: 26.4 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

fyemane/Bidirectional-visitor-counter

A bidirectional room visitor counter using schematic capture and AHDL on Intel Quartus Prime using an Altera CPLD

Language: HTML - Size: 646 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Multimedia-Processing/Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Language: Verilog - Size: 181 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 2

jpenolio75/smp8

An implementation of a simple 8-bit microprocessor on an Altera DE2-115 board for UNLV CpE 300L Digital Systems Architecture and Design final project.

Language: Verilog - Size: 8.79 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

GeoKrom/UoI-Digital-Design-II-course

Lab exercises on digital circuit design using Altera Quartus 9.1sp2

Language: VHDL - Size: 20.7 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

AndrejGobeX/FlagQuiz

Altera Quartus Project for Fundamentals of Computer Engineering subject

Size: 5.59 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

Related Keywords
altera-quartus 9 fpga 4 digital-design 3 vhdl 3 altera-fpga 3 verilog-hdl 3 verilog 2 xilinx-vivado 2 vlsi-design 2 vlsi 2 serialization 2 serial-port 2 rtl-design 2 rtl 2 register-transfer-level 2 power-gating 2 low-power 2 fpga-programming 2 comparator 2 digital 1 digital-logic 1 digital-logic-design 1 hdl 1 learn 1 soc-kit 1 systemverilog 1 vhdl-verilog 1 xilinx 1 xilinx-fpga 1 de2-115 1 microprocessor 1 altera-cyclone-ii 1 digital-circuits 1 game 1 altera-cyclone-v-sockit 1 altera-cyclone-iii-de0 1 altera-cyclone 1 intel 1 falstad 1 cpld 1 vhdl-examples 1 unam 1 quartus2 1 quartus 1 altera 1 vhdl-code 1 synchronous-counter 1 modelsim 1 altera-de1 1 logic-circuit 1