GitHub topics: altera-fpga
drandyhaas/HaasoscopePro
Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope
Language: Verilog - Size: 447 MB - Last synced at: about 5 hours ago - Pushed at: about 7 hours ago - Stars: 137 - Forks: 27
robseb/HPS2FPGAmapping
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
Language: Verilog - Size: 11 MB - Last synced at: 7 days ago - Pushed at: almost 4 years ago - Stars: 37 - Forks: 13
pourya-kgp/HBAonFPGA
Implementation of Hardware Bee Algorithm (HBA) on FPGA for solving the Traveling Salesperson Problem (TSP) (M.S. Thesis)
Language: MATLAB - Size: 25.5 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
ultraembedded/openlogicbit
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
Language: Verilog - Size: 606 KB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 133 - Forks: 18
Jjateen/Snake-Game-Verilog
This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.
Language: Verilog - Size: 8.63 MB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 2 - Forks: 0
mbtaylor1982/ReSDMAC
Verilog code to replace the Commodore SDMAC found in the A3000
Language: Verilog - Size: 160 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 40 - Forks: 3
EngineerMichael/ModelSim-Altera-Project-Electronics-
⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.
Size: 25.4 KB - Last synced at: about 2 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 0
mrLSD/fpga
Research & Development FPGA projects for different boards
Language: GLSL - Size: 420 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 0
WassimHedfi/Nios-II-IP-core
This project involves configuring a NIOS II softcore processor on the Altera DE10-Lite FPGA using Quartus Prime. It includes the creation of a custom Board Support Package (BSP), hardware abstraction layer (HAL), and drivers to optimize processor performance.
Language: Verilog - Size: 42.8 MB - Last synced at: 26 days ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
ThuyPham/FPGA-Toturial
FPGA Tutorial Basic thuypx.com
Language: VHDL - Size: 14.6 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
LojananS/305-team-21
Team 21 - Mini-Project
Language: VHDL - Size: 482 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
abphilip-vit/CollegeP1
College - Digital Lock
Language: Verilog - Size: 4.53 MB - Last synced at: 11 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
abphilip-vit/College2
College - Lab Tasks of Digital Circuit Design
Language: HTML - Size: 29.1 MB - Last synced at: 11 months ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0
nobotro/my-created-fpga-verilog-samples
my created fpga verilog samples.
Language: Verilog - Size: 4.33 MB - Last synced at: 11 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
MKme/fpga
FPGA and CPLD programming, tutorials and information I figure out.
Language: VHDL - Size: 4.37 MB - Last synced at: 12 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0
asankaSovis/Position_Detection
📌 The idea of this project is to build a system that uses the existing lights to detect the location of a user within an indoor environment. For this, we can use Visible Light Communication (VLC) technology. The basic concept is to have four LEDs transmitting their IDs one after the other at fixed intervals.
Language: Verilog - Size: 5.09 MB - Last synced at: 24 days ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 1
arnaldojr/Robot-FPGA
Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.
Language: VHDL - Size: 25.4 KB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0
gaikwadabhishek/flappy-bird-fpga-vhdl
Flappy Bird on FPGA using VHDL
Language: HTML - Size: 119 KB - Last synced at: 18 days ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
pokitoz/DE0_SoC_altera_config
Language: C - Size: 133 KB - Last synced at: about 1 year ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 1
Sayeed97/LCD-Controller
A firmware was written in VHDL to display all the characters from the ASCII table to the display.
Language: VHDL - Size: 542 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
lazyoracle/vhdl-processor
An 8-bit processor in VHDL based on a simple instruction set
Language: VHDL - Size: 209 KB - Last synced at: 10 months ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 0
Multimedia-Processing/Digital-Logic-Design
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
Language: Verilog - Size: 181 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 2
rafafigueredoviana/RISCV_MCU_CYCLONEV
A basic implementation of the RISCV core into a DE10nano FPGA board.
Language: SystemVerilog - Size: 58.9 MB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 6 - Forks: 5
Chrisdeleon91/Altera-DE1-VGA-Interface
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
Language: VHDL - Size: 8.2 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
nikolovjovan/FPGAParallelSorting 📦
Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.
Language: VHDL - Size: 1.97 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0
william-hazem/LASD
Laboratório de Arquitetura de Sistemas Digitais, ministrado pelo professor Rafael Bezerra Correia Lima. Foram desenvolvidos 8 requisitos de hardware, 1 requisito de software e 1 projeto de disciplina que totalizam 10 Sprints. A arquitetura de sistemas implementada é baseada em MIPS 8 bits, e desenvolvidos e testados na FGPA Ciclone II EP2C35F672C6
Language: Verilog - Size: 13.5 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0
alvarezpj/single-cycle-cpu
VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls
Language: VHDL - Size: 156 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 5
HaochengBillYang/ece385
ECE385 @ UIUC FA22
Language: Verilog - Size: 199 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0
atmughrabi/AccelGraph
Graph Processing Framework that supports || OpenMP || CAPI
Language: SystemVerilog - Size: 1.3 GB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0
samdejong86/Arria-V-ADC-Ethernet
Transfers data from an ADC to a PC via ethernet
Language: Verilog - Size: 23.6 MB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 3 - Forks: 2
mohamedtareq24/4_Channel_Logic_Analyzer
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA
Language: Verilog - Size: 139 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
MatheusAndrade1/Digital-Clock-in-VHDL
Digital clock in VHDL, on Altera Cyclone IV FPGA Board A-C4E6. This work was presented on PLP discipline during electrical engineer course at Mackenzie Presbyterian University.
Language: VHDL - Size: 1.28 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0
mateuspinto/FPGA_Verilog_Ballot_Box-TP2-ISL-UFV
Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.
Language: Verilog - Size: 10.1 MB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 4 - Forks: 1
yasnakateb/Blinky
💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board
Language: Verilog - Size: 42 KB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0
yvan674/Hardware-Praktikum
Hardware Praktikum at Uni Freiburg
Language: VHDL - Size: 3.27 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0
M-Schrapel/FPGA-Function-Generator
A scalable and freely configurable function generator in VHDL
Language: VHDL - Size: 67.7 MB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
briansune/Altera-Cyclone-V-HDMI
Verilog based HDMI for Cyclone V or Altera series
Language: Verilog - Size: 1.4 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
Terminatorjjjjj/NTUEE-DCLAB-Materials
This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).
Language: SystemVerilog - Size: 65.4 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 5 - Forks: 5
ThePituLegend/RISC-V_DE10-Nano
This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.
Language: Verilog - Size: 6.46 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 1
lstolcman/bachelor-thesis
Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract
Language: Verilog - Size: 228 MB - Last synced at: 8 days ago - Pushed at: almost 7 years ago - Stars: 4 - Forks: 1
Davide-DD/mastermind
FPGA implementation of the popular logic game using VHDL and Altera DE1
Language: VHDL - Size: 7.64 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 7 - Forks: 1
GeoKrom/UoI-Digital-Design-II-course
Lab exercises on digital circuit design using Altera Quartus 9.1sp2
Language: VHDL - Size: 20.7 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0
t4rcisio/Arquivos_Verilog
Processador nano-Risc, controlaor de display, e muito mais...
Language: Verilog - Size: 5.15 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
andrsmllr/de0_atlas_soc_devbrd
Play and learn with the Terasic DE0-Atlas/Nano-SoC Kit featuring a Altera/Intel Cyclone V 5CSEMA4U23C6N FPGA with integrated dual-core ARM Cortex-A9.
Language: Verilog - Size: 30.3 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
chkrr00k/hex-controller
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
Language: VHDL - Size: 6.84 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0
chkrr00k/sram-controller
A simple sram controller and test for the altera DE1 FPGA board
Language: VHDL - Size: 15.6 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 2
frankshc/guitar_amp_sim
Guitar amp sim for Altera DE1-SoC NIOS2
Language: Assembly - Size: 2.29 MB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 1
nlevnaut/mips_proc
A MIPS processor implementation for the Altera DE2 Cyclone II FPGA dev board
Language: Verilog - Size: 780 KB - Last synced at: 5 months ago - Pushed at: over 8 years ago - Stars: 0 - Forks: 2
