GitHub topics: riscv-assembly
OpenMachine-ai/tinyfive
TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples
Language: Python - Size: 355 KB - Last synced at: 8 days ago - Pushed at: over 1 year ago - Stars: 58 - Forks: 8
XUANTIE-RV/csi-nn2
An optimized neural network operator library for chips base on Xuantie CPU.
Language: C - Size: 16.1 MB - Last synced at: 11 days ago - Pushed at: 10 months ago - Stars: 90 - Forks: 40
OpenMachine-ai/HuggingFive
HuggingFive 🖐️ is a collection of ML functions and libraries written in RISC-V assembly and C.
Size: 76.2 KB - Last synced at: 10 days ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 0
martinKindall/risc-v-single-cycle
A Single Cycle Risc-V 32 bit CPU
Language: SystemVerilog - Size: 36.1 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 38 - Forks: 2
wooster0/rva
RISC-V Assembler with execution of code at assembly-time
Language: Zig - Size: 39.1 KB - Last synced at: about 7 hours ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0
cgyurgyik/riscv-assembly
Implementation of common functions using RISC-V assembly.
Language: Assembly - Size: 79.1 KB - Last synced at: 17 days ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 3
schorrm/arm2riscv
Arm AArch64 to RISC-V Transpiler
Language: Python - Size: 2.34 MB - Last synced at: 10 days ago - Pushed at: almost 5 years ago - Stars: 33 - Forks: 3
JN513/Risco-5S
RISC-V Simulator with RV32IM implementation, built during a few days off.
Language: C - Size: 656 KB - Last synced at: 21 days ago - Pushed at: 6 months ago - Stars: 4 - Forks: 0
muhammadtalhasami/riscv-assembly
This repo is the learning journey of the riscv assembly language. you will learn how to write the high level code in to the riscv assembly code.
Language: Assembly - Size: 10.7 KB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
phoeniX-Digital-Design/AssembleX
RISC-V Assembly Software Assistant
Language: Python - Size: 112 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 5 - Forks: 1
rafinhadufluxo/2021.2-Org-Trabalho1-1
Development of a naval battle game in assembly (risc-v)
Size: 815 KB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
MaxBubblegum47/Tutorato_Architettura
Materiale tutorato Architettura dei Calcolatori. Esercizi sul simulatore logisim e rars in assembly per RISCV
Language: Assembly - Size: 25.4 KB - Last synced at: about 1 month ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0
rizwan3d/SharpRISCV
SharpRISCV is an implementation of RISC-V assembly in C#. First RISC V Assembly that build windows executable file
Language: C# - Size: 11.9 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 24 - Forks: 4
byungwoo733/My_RARS-RISCV-
My_RARS(RISCV Assembly) with Bitmap Display by RISCV Instructions (RISCV SIMD ISA)
Size: 12.8 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
Shahriar-0/Computer-Architecture-Course-Projects-S2023
Verilog implementation of a DFS search and RISC-V processor in Single-Cycle, Multi-Cycle and Pipeline
Language: Verilog - Size: 13.3 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 6 - Forks: 1
SpinSpinSugar/riscv-check
Small test project to analyse RISC-V bitmanip extension
Language: Python - Size: 50.8 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
technoblogy/lisp-riscv-assembler
A RISC-V assembler written in Lisp.
Language: Common Lisp - Size: 7.81 KB - Last synced at: 9 months ago - Pushed at: about 5 years ago - Stars: 37 - Forks: 3
splinedrive/lets_build_a_compiler_for_riscv
A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
Language: C - Size: 2.65 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 21 - Forks: 4
silver-ymz/rvsim
A toy riscv32 5-stage pipeline simulator
Language: Rust - Size: 42 KB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
qingpeng9802/build-maix-bit-k210-bare-metal-debug-dev-env
This tutorial is designed to help you build a bare metal debugging and development environment for Sipeed Maix Bit (Kendryte 210).
Size: 1.22 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 14 - Forks: 1
qingpeng9802/port-riscv-asm-from-venus-to-k210
This tutorial is designed to help you convert Venus RISC-V Assembly to real chip Kendryte 210 (K210) RISC-V Assembly.
Size: 22.5 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1
qingpeng9802/minijava-to-k210-riscv-compiler
This Compiler can translate MiniJava into K210 RISC-V assembly.
Language: Assembly - Size: 395 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 1
ThePituLegend/RISC-V_DE10-Nano
This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.
Language: Verilog - Size: 6.46 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 1
xigh/libriscv-rs
RISCV decoder / encoder library written in Rust
Language: Rust - Size: 23.4 KB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0
imlyzh/riscv-process-rs
This is a RISC-V process library
Language: Rust - Size: 137 KB - Last synced at: 16 days ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0
SoniSiddharth/RISCV_Three_Stage Fork of adityatripathiiit/RISCV_Three_Stage
RISC-V 3 stage in-order pipeline in verilog
Size: 1.15 MB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0
m-herrera/riscv-image-processing
Riscv assembly implementation of an image processing program, using convolution of 3x3 kernels.
Language: Assembly - Size: 137 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 1
