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GitHub / Shahriar-0 / Computer-Architecture-Course-Projects-S2023

Verilog implementation of a DFS search and RISC-V processor in Single-Cycle, Multi-Cycle and Pipeline

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Shahriar-0%2FComputer-Architecture-Course-Projects-S2023

Stars: 6
Forks: 1
Open issues: 1

License: mit
Language: Verilog
Size: 13.3 MB
Dependencies parsed at: Pending

Created at: about 2 years ago
Updated at: over 1 year ago
Pushed at: about 1 year ago
Last synced at: about 1 year ago

Topics: dfs, modelsim, riscv-assembly, riscv-cpu, verilog

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