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GitHub topics: riscv-cpu

dpretet/friscv

RISCV CPU implementation in SystemVerilog

Language: Coq - Size: 4.1 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 15 - Forks: 4

Shahriar-0/Computer-Architecture-Course-Projects-S2023

Verilog implementation of a DFS search and RISC-V processor in Single-Cycle, Multi-Cycle and Pipeline

Language: Verilog - Size: 13.3 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 6 - Forks: 1

lild4d4/usm_microcontroller_v1

Undergraduate level RISC-V microcontroller

Language: SystemVerilog - Size: 201 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Related Keywords
riscv-cpu 3 fpga 2 riscv 2 verilog 2 xilinx-fpga 1 xilinx 1 utfsm 1 riscv32 1 nexys4ddr 1 microcontroller 1 fpga-projects 1 entry-level 1 cpu 1 amd 1 riscv-assembly 1 modelsim 1 dfs 1 systemverilog 1 rv32i 1 risc-v 1 fpga-soc 1 crossbar 1 axi4-protocol 1 axi4 1 assembler 1 asic-design 1 asic 1