GitHub topics: rv32i

Repositories

calint/tang-nano-9k--riscv--cache-psram

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

Language: SystemVerilog - Size: 5.65 MB - Last synced at: about 20 hours ago - Pushed at: about 21 hours ago - Stars: 28 - Forks: 1

sysprog21/shecc

A self-hosting and educational C optimizing compiler

Language: C - Size: 1.94 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,214 - Forks: 129

rafaelcalcada/rvx

RISC-V microcontroller IP core developed in Verilog

Language: Verilog - Size: 191 MB - Last synced at: 1 day ago - Pushed at: 11 days ago - Stars: 173 - Forks: 22

WangXuan95/USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Language: SystemVerilog - Size: 62.2 MB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 398 - Forks: 79

markelmencia/rvik

RV32i assembler and simulator

Language: Java - Size: 530 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

calint/rust_rv32i_os

Bare metal Rust for the RV32I in project "tang-nano-9k--riscv--cache-psram"

Language: Rust - Size: 269 KB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 2 - Forks: 1

Alessandro-Salerno/ezld

Tiny, simple, and portable ELF linker

Language: C - Size: 537 KB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 3 - Forks: 0

AleksandarLilic/ama-riscv-sim

C++ Instruction Set Simulator for RISC-V RV32IMC & custom SIMD instructions with cache and branch predictor models, C/ASM workloads, and Python analysis tools

Language: C++ - Size: 22 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 2 - Forks: 1

GabbedT/ApogeoRV

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

Language: SystemVerilog - Size: 6.96 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 16 - Forks: 2

maikmerten/spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Language: C - Size: 714 KB - Last synced at: 15 days ago - Pushed at: almost 3 years ago - Stars: 69 - Forks: 13

ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

Language: Verilog - Size: 2.98 MB - Last synced at: 20 days ago - Pushed at: over 3 years ago - Stars: 980 - Forks: 164

saursin/riscv-atom

An open-source 32-bit RISC-V soft-core processor

Language: C++ - Size: 2.88 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 33 - Forks: 15

KietLe11/KLP32-RISCV

This project implements a simple RISC-V processor for FPGAs. It supports the RV32I base instruction set and is designed for educational and experimental purposes.

Language: Verilog - Size: 407 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 4 - Forks: 0

ubaidrmn/RISC-V-assembly

RISC-V assembly code I wrote as part of my COAL course at UIT University.

Size: 14.6 KB - Last synced at: 22 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

ultraembedded/riscv

RISC-V CPU Core (RV32IM)

Language: Verilog - Size: 5.27 MB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 1,398 - Forks: 251

syntacore/scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Language: SystemVerilog - Size: 5.49 MB - Last synced at: 30 days ago - Pushed at: 5 months ago - Stars: 904 - Forks: 284

calint/tang-nano-20k--riscv--cache-sdram

RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM and flash

Language: SystemVerilog - Size: 9.15 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 7 - Forks: 0

AleksandarLilic/ama-riscv

Verilog RISC-V RV32I 5-stage single issue core

Language: SystemVerilog - Size: 909 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

yoshiyuki-takeda/RISC-V_SOBAKO-CORE

adapted small fpga and portability any device RISC-V core

Language: Verilog - Size: 287 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

martinKindall/risc-v-single-cycle

A Single Cycle Risc-V 32 bit CPU

Language: SystemVerilog - Size: 36.1 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 38 - Forks: 2

stnolting/riscv-gcc-prebuilt 📦

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

Language: Shell - Size: 90.8 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 98 - Forks: 10

arhamhashmi01/rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Language: Verilog - Size: 357 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 10 - Forks: 0

imchristina/risky

Simple RV32I Verilog Core

Language: Verilog - Size: 24.4 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Language: SystemVerilog - Size: 432 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 35 - Forks: 2

mattbucknall-oss/rv32im-gnu-toolchain

Simple bash script for building GNU riscv32-unknown-elf-gcc newlib toolchain.

Language: Shell - Size: 34.2 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

LockBlock-dev/Vector

RISC-V ISA emulator

Language: C++ - Size: 41 KB - Last synced at: 13 days ago - Pushed at: 3 months ago - Stars: 6 - Forks: 0

Khallil973/RV32I-Core

RV32I 5-Stage Pipelined CPU

Language: Verilog - Size: 218 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

Davidls10/riscv-pipelined-sv

Simple RISC-V Pipelined processor implemented on SystemVerilog.

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

calint/tang-nano-20k--riscv

Language: Verilog - Size: 180 KB - Last synced at: about 2 months ago - Pushed at: 4 months ago - Stars: 4 - Forks: 0

Kokbddjkejsb/dOrv32

5-stage pipeline risc-v cpu

Size: 18.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

DvvCz/dasm

Tiny dynamic assembly library for x86/amd64/rv32i/rv64i

Language: Rust - Size: 55.7 KB - Last synced at: 14 days ago - Pushed at: 2 months ago - Stars: 6 - Forks: 1

zhuocheng2004/parabolium

A Simple RISC-V Processor

Language: C - Size: 193 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

barrettotte/thoth-rv32

Single cycle RISC-V core supporting most of RV32I

Language: Verilog - Size: 19.5 KB - Last synced at: 26 days ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

NignetShark/lagarisc32

A FPGA softcore RISCV 5 stages

Language: VHDL - Size: 61.5 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

muhammadtalhasami/RV32I_Single_Cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Language: Verilog - Size: 168 KB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0

trolund/risc-v-instruction-set-simulator 📦

A basic RISC-V simulator, implementing the RV32I Instructions.

Language: Assembly - Size: 5.64 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

aignacio/nox

RISC-V Nox core

Language: C - Size: 26.3 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 56 - Forks: 6

davidli218/rv32ias

Assembler for the RISC-V RV32I instruction set

Language: Python - Size: 57.6 KB - Last synced at: about 1 month ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

davidli218/basic-rv32i-cpu

Basic RV32I RISC-V CPU Implementation

Language: SystemVerilog - Size: 39.1 KB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

Language: Verilog - Size: 56.6 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

meeeeet/5-Stage-Pipelined-RISC-V-Processor

Language: Verilog - Size: 4.59 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

kiclu/arp

RISC-V based microprocessor system for Altera DE0 FPGA board

Language: VHDL - Size: 56.6 MB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 0

tvlad1234/rv32adventure

Becoming acquainted with the RISC-V ISA by writing an emulator

Language: C - Size: 34.2 KB - Last synced at: 23 days ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 1

muhammadtalhasami/rv32I_single_cycle_logisim

An implementation of rv32i single cycle processor on logisim

Size: 149 KB - Last synced at: 24 days ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 1

arhamhashmi01/rv32i-sv

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

Language: SystemVerilog - Size: 38.1 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 2

RISCuinho/core

**RISC**uinho - A scratch in the possibilities in the universe of microcontrollers

Size: 3.21 MB - Last synced at: 6 months ago - Pushed at: over 2 years ago - Stars: 20 - Forks: 4

tlatonf/venmac

The Laboratory for Computer Architecture (EE3043)

Language: SystemVerilog - Size: 516 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

Language: Verilog - Size: 115 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

simonamtoft/RISCV-Simulator

A simulator of RISC-V instruction set written in Java

Language: Java - Size: 387 KB - Last synced at: 9 months ago - Pushed at: over 6 years ago - Stars: 7 - Forks: 2

Ammar-Bin-Amir/RV32I_5-Stage_Pipelined_CPU

Processor Design of RV32I 5-Stage Pipelined CPU

Language: SystemVerilog - Size: 170 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

dpretet/friscv

RISCV CPU implementation in SystemVerilog

Language: Coq - Size: 4.1 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 15 - Forks: 4

gafert/Apate

A graphical and educational processor simulator based on the RISC-V instruction set architecture

Language: TypeScript - Size: 10.8 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 10 - Forks: 3

Ammar-Bin-Amir/RV32I_Single_Cycle_CPU

Processor Design of RV32I Single Cycle CPU

Language: SystemVerilog - Size: 590 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

donn/Oak 📦

Aggregate assembler and simulator.

Language: Swift - Size: 79.1 KB - Last synced at: 12 months ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

akastoras/riscv

RISC-V implementation for Parallel Computer Architecture class.

Language: Assembly - Size: 2.01 MB - Last synced at: 6 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 1

Zvorky/Cyclist

RISC-V Performance Measurement Tool

Language: Python - Size: 93.8 KB - Last synced at: 16 days ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

nobotro/fpga_riscv_cpu

fpga verilog risc-v rv32i cpu

Language: Verilog - Size: 97.3 MB - Last synced at: 11 months ago - Pushed at: about 2 years ago - Stars: 8 - Forks: 2

AleksandarLilic/ama-riscv-perfsim

Cycle Accurate C++ performance model of the ama-riscv core

Language: C++ - Size: 219 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

HarieshAnbalagan/RV32I

Minimalistic RV32I RISC-V Processor in System Verilog

Language: SystemVerilog - Size: 392 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

Eremeir/csci463

CSCI463

Language: C++ - Size: 96.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

joscarvalho/Pipeline-RISCV

5-stage pipelined RISC-V soft-core processor implemented in Verilog. It is based on RV32i Instruction Set.

Language: Verilog - Size: 480 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

ErikNikolajsen/RISC-V-instruction-set-simulator

RISC-V instruction set simulator

Language: Java - Size: 38.1 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

Engineer-Ayesha-Shafique/RISC-V-Single-Cycle-Processor

This is a Single Cycle processor running the RV32I implementation, hence a 32-bit CPU, written in SystemVerilog.

Language: SystemVerilog - Size: 8.54 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

AllenHeartcore/ECE411_UIUC23fa 📦

Ziyuan Chen, ECE411 @ UIUC 23FA

Language: Verilog - Size: 16.2 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

AngeloJacobo/RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Language: Verilog - Size: 6.66 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 29 - Forks: 0

paulsonkantony/risk-five

A Verilog based implementation of the unprivileged RV32I ISA

Language: Verilog - Size: 98.4 MB - Last synced at: 9 months ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 2

coronensis/rival

Rival - A RISC-V RV32I CPU

Language: VHDL - Size: 37.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 2

jjgar11/Digital-2

Desarrollo para la materia de Electronica Digital 2

Language: Verilog - Size: 15.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

RISCV-MYTH-WORKSHOP/riscv-myth-workshop-sep23-fayizferosh

5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD

Language: Verilog - Size: 699 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

FelipeFFerreira/ITA-CORES

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

Language: Verilog - Size: 186 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

xarc/harv

HARV - HArdened Risc-V

Language: VHDL - Size: 109 KB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 1

lwshowl/RISCV

synthesisable verilog rv32i instruction set cpu

Language: Verilog - Size: 3.01 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

sysprog21/rv32emu-legacy 📦

RISC-V RV32I[MA] emulator with ELF support

Language: C - Size: 32.2 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 46 - Forks: 18

Related Keywords

rv32i 117 risc-v 88 riscv 39 verilog 35 cpu 23 fpga 22 riscv32 18 systemverilog 11 computer-architecture 9 rv32im 9 assembler 8 verilator 7 emulator 6 processor 6 simulator 6 pipeline-processor 6 linux 6 single-cycle-processor 6 rtl 6 pipeline 6 vhdl 5 c 5 asic 5 assembly 5 riscv-simulator 4 rv32 4 cpp 4 risc-processor 4 risc 4 hardware-designs 4 tl-verilog 4 5-stage-pipeline 4 softcore 4 core 4 hdl 3 rv32imc 3 elf 3 gcc 3 5-stage-pipelined-processor 3 gtkwave 3 microprocessor 3 rv32i-processor 3 processor-architecture 3 assembly-language 3 altera 3 elf-parser 3 microcontroller 3 verilog-hdl 3 system-on-chip 3 digital-circuit-design 3 fpga-programming 2 simulation 2 qemu 2 verification 2 embedded 2 xilinx 2 tang-nano-20k 2 basys3 2 microprocessors 2 riscv-assembly 2 microarchitecture 2 asic-design 2 riscv-emulator 2 risc-v-assembly 2 chisel 2 pipelines 2 processor-design 2 system-verilog 2 rv64i 2 baremetal 2 tang-nano-9k 2 single-cycle 2 mcu 2 logisim 2 embedded-systems 2 toolchain 2 instruction-set-simulator 2 cli 2 inorder 2 rust 2 rtl-design 2 fpga-soc 2 bare-metal-programming 2 riscv-linux 2 pipelined-processors 2 in-order 2 branch-prediction 2 longan-nano 2 zicsr 2 ice40 2 soc 2 fpga-risc-v 1 quartus 1 tang-nano-1k 1 physical-design-automation 1 rom-execution 1 fault-tolerance 1 physical-design 1 framework 1 performance-analysis 1