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GitHub topics: rv32imc

syntacore/scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Language: SystemVerilog - Size: 5.49 MB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 904 - Forks: 284

KASIRGA-KIZIL/tekno-kizil

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Language: Verilog - Size: 1.04 GB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 139 - Forks: 11

rob-ng15/Silice-Playground

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

Language: C - Size: 640 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 34 - Forks: 5

djzenma/RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

Language: Verilog - Size: 3.19 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 11 - Forks: 2

Related Keywords
risc-v 4 rv32imc 4 rv32i 3 verilog 3 fpga 2 riscv 2 rtl 2 cpu 2 pipeline-processor 2 pipeline-cpu 1 hdl 1 ulx3s 1 rv32im 1 rv32 1 j1-cpu 1 forth 1 fomu 1 risc 1 risc-processor 1 riscv-simulator 1 riscv32 1 riscv32im 1 verilog-code 1 verilog-hdl 1 verilog-snippets 1 de10nano 1 verification 1 teknofest 1 processor 1 openlane 1 llvm 1 in-order 1 coremark 1 computer-architecture 1 clang 1 asic 1 rv32emc 1 rv32e 1 ip 1 core 1