GitHub topics: riscv32

Repositories

weizhiao/rust-elfloader

A loader capable of loading and relocating various forms of ELF files from memory or files.

Language: Rust - Size: 454 KB - Last synced at: about 14 hours ago - Pushed at: about 14 hours ago - Stars: 43 - Forks: 10

ccattuto/riscv-python

RISC-V Emulator in pure Python (RV32I, machine mode, Newlib support)

Language: Python - Size: 407 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 3 - Forks: 0

LekKit/RVVM

The RISC-V Virtual Machine

Language: C - Size: 3.79 MB - Last synced at: 1 day ago - Pushed at: 2 days ago - Stars: 1,043 - Forks: 75

saursin/riscv-atom

An open-source 32-bit RISC-V soft-core processor

Language: C++ - Size: 2.9 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 34 - Forks: 15

JN513/Grande-Risco-5

Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.

Language: SystemVerilog - Size: 521 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 7 - Forks: 0

tommythorn/yarvi

Yet Another RISC-V Implementation

Language: Roff - Size: 2.82 MB - Last synced at: about 18 hours ago - Pushed at: 7 months ago - Stars: 92 - Forks: 24

chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

Language: SystemVerilog - Size: 17.6 MB - Last synced at: 5 days ago - Pushed at: almost 2 years ago - Stars: 870 - Forks: 227

jesseopdenbrouw/thuas-riscv

The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbb Zbs Sdext Sdtrig microcontroller

Language: C - Size: 20 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 5 - Forks: 1

fedejinich/bitvmx_pkmn_bttl

A Bitcoin-Pokemon game using BitVMX

Language: Zig - Size: 381 KB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 2 - Forks: 0

sysprog21/rv32emu

Compact and Efficient RISC-V RV32I[MAFC] emulator

Language: C - Size: 11.2 MB - Last synced at: 5 days ago - Pushed at: 29 days ago - Stars: 470 - Forks: 112

markelmencia/rvik

RV32i assembler and simulator

Language: Java - Size: 530 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

developeruche/riscv-evm-experiment

The RISC-V EVM Experiment aims to bridge the gap between the RISC-V instruction set architecture and the Ethereum Virtual Machine (EVM). By integrating RISC-V with the EVM, we seek to create a more efficient, secure, and scalable blockchain VM platform. With the vast target diversity of the RISC-V instruction set architecture.

Language: Rust - Size: 474 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

chipsalliance/Cores-VeeR-EL2

VeeR EL2 Core

Language: SystemVerilog - Size: 33.5 MB - Last synced at: about 10 hours ago - Pushed at: about 10 hours ago - Stars: 274 - Forks: 82

SaiManojGubbala/RISC-V

A 32 Bit RISC-V Processor Implementation in Verilog

Language: Verilog - Size: 4.4 MB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 3 - Forks: 0

svenssonjoel/lispBM

An interpreter for a concurrent lisp with message-passing and pattern-matching.

Language: C - Size: 25.5 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 102 - Forks: 11

cahirwpz/mimiker

Simple unix-like operating system for education and research purposes

Language: C - Size: 6.94 MB - Last synced at: 9 days ago - Pushed at: 8 months ago - Stars: 306 - Forks: 48

harisraharjo/rivet

RISCV-Inspired 32 bit Virtual Execution Tool

Language: Rust - Size: 324 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

OpenMachine-ai/tinyfive

TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples

Language: Python - Size: 355 KB - Last synced at: 11 days ago - Pushed at: over 1 year ago - Stars: 58 - Forks: 8

mrLSD/riscv-fs

F# RISC-V Instruction Set formal specification

Language: F# - Size: 148 KB - Last synced at: 5 days ago - Pushed at: 8 months ago - Stars: 282 - Forks: 14

dpretet/axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

Language: SystemVerilog - Size: 438 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 142 - Forks: 27

google/esh

UART based embedded shell for embedded systems. Intended to be used for learning, experimenting and diagnostics.

Language: C - Size: 11.4 MB - Last synced at: 7 days ago - Pushed at: about 1 year ago - Stars: 269 - Forks: 51

tvlad1234/pico-rv32ima

Running Linux on RP2040 with the help of RISC-V emulation

Language: C - Size: 12.3 MB - Last synced at: 19 days ago - Pushed at: 10 months ago - Stars: 272 - Forks: 19

jesse-r-s-hines/RISC-V-Graphical-Datapath-Simulator

This is a web-based graphical simulator for a simple 32-bit, single-cycle implementation of RISC-V.

Language: TypeScript - Size: 9.8 MB - Last synced at: 21 days ago - Pushed at: about 1 month ago - Stars: 17 - Forks: 2

SKpro-glitch/RISCV-Processor-ASIC

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

Language: Verilog - Size: 138 KB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

KietLe11/KLP32-RISCV

This project implements a simple RISC-V processor for FPGAs. It supports the RV32I base instruction set and is designed for educational and experimental purposes.

Language: Verilog - Size: 407 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 4 - Forks: 0

ultraembedded/exactstep

Instruction set simulator for RISC-V, MIPS and ARM-v6m

Language: C++ - Size: 970 KB - Last synced at: 20 days ago - Pushed at: over 3 years ago - Stars: 95 - Forks: 19

Imtjl/io-systems

Low-level I/O systems: OpenSBI, bare-metal C, Linux drivers.

Language: C - Size: 8.56 MB - Last synced at: 27 days ago - Pushed at: 28 days ago - Stars: 0 - Forks: 0

OpenMachine-ai/HuggingFive

HuggingFive 🖐️ is a collection of ML functions and libraries written in RISC-V assembly and C.

Size: 76.2 KB - Last synced at: 13 days ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 0

KUNAL-KUMAR-SINGH-Coder/RV32I

Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.

Language: Verilog - Size: 111 KB - Last synced at: 30 days ago - Pushed at: 30 days ago - Stars: 0 - Forks: 0

jserv/rv32jit

JIT-accelerated RISC-V instruction set simulator

Language: C++ - Size: 171 KB - Last synced at: 4 days ago - Pushed at: over 1 year ago - Stars: 33 - Forks: 8

leecannon/zig-sbi

Zig wrapper around the RISC-V SBI specification

Language: Zig - Size: 135 KB - Last synced at: 11 days ago - Pushed at: about 2 months ago - Stars: 14 - Forks: 4

agra-uni-bremen/symex-vp

A concolic testing engine for RISC-V embedded software with support for SystemC peripherals

Language: C++ - Size: 31.7 MB - Last synced at: 14 days ago - Pushed at: over 1 year ago - Stars: 23 - Forks: 5

Samulix20/GaZmusino

A tiny, open-source RISC-V processor designed for learning and experimentation.

Language: Assembly - Size: 39.1 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

inpyjama/c-ninja-listings

Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.

Language: Makefile - Size: 3.17 MB - Last synced at: 16 days ago - Pushed at: 6 months ago - Stars: 1 - Forks: 7

skyzh/RISCV-Simulator

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

Language: C++ - Size: 483 KB - Last synced at: 25 days ago - Pushed at: almost 5 years ago - Stars: 201 - Forks: 18

Kristoff-starling/ProjectN-CPU

Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU

Language: C++ - Size: 1.39 MB - Last synced at: 23 days ago - Pushed at: over 3 years ago - Stars: 14 - Forks: 3

Hammersamatom/brv

A WIP RV32I emulator, aiming to eventually support RV64I + MAFDC extensions

Language: C++ - Size: 1.02 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

martinKindall/risc-v-single-cycle

A Single Cycle Risc-V 32 bit CPU

Language: SystemVerilog - Size: 36.1 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 38 - Forks: 2

Shuregg/riscv-simple-cpu

Creating a risc-v processor

Language: SystemVerilog - Size: 4.58 MB - Last synced at: 27 days ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

wooster0/rva

RISC-V Assembler with execution of code at assembly-time

Language: Zig - Size: 39.1 KB - Last synced at: 3 days ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

risc0/risc0-lean4

A model of the RISC Zero zkVM and ecosystem in the Lean 4 Theorem Prover

Language: Lean - Size: 3.14 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 62 - Forks: 4

drom/awesome-riscv

😎 A curated list of awesome RISC-V implementations

Size: 27.3 KB - Last synced at: 5 days ago - Pushed at: about 2 years ago - Stars: 134 - Forks: 13

pixelspark/rv32jit

A RISC-V (rv32imc) assembler for JITing on the ESP32

Language: Rust - Size: 77.1 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0

rihib/learn-os-on-weekends

Original material for learning OS

Language: C - Size: 96.7 KB - Last synced at: 21 days ago - Pushed at: 3 months ago - Stars: 5 - Forks: 5

Seif-Sallam/Disassembler

The project implements the disassemble of the RISCV32IC instructions from binary to actual text instructions.

Language: C++ - Size: 395 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

dernatsch/nrv32emu

RISC-V 32 emulator with not a lot of features.

Language: Rust - Size: 5.27 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

physical-computation/sunflower-embedded-system-emulator

Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.

Language: C - Size: 305 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 25 - Forks: 218

lupyuen/nuttx-bl602 Fork of apache/nuttx

Apache NuttX OS as featured in "The RISC-V BL602 Book"

Language: C - Size: 199 MB - Last synced at: about 3 hours ago - Pushed at: 1 day ago - Stars: 10 - Forks: 1

Samulix20/riscv-vhdl

An academic RISC-V processor, implemented in VHDL, capable of running FreeRTOS

Language: C - Size: 340 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 2

lupyuen/nuttx-rust-app

Rust Apps for Apache NuttX RTOS and QEMU RISC-V

Language: Rust - Size: 78.1 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

jesseopdenbrouw/riscv-rv32 📦

A synthesizable RISC-V RV32IM microcontroller written in VHDL

Language: C - Size: 14.3 MB - Last synced at: 13 days ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0

rnayabed/taurus

SDK for CDAC Vega Processors

Language: C - Size: 5.04 MB - Last synced at: 18 days ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 4

rvangelse/RISC-V

Ejercicios de practica implementados en RISC-V Assembly

Language: Assembly - Size: 24.4 KB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

mongrelgem/RISCY

Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs

Language: VHDL - Size: 395 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 13 - Forks: 4

snnbyyds/semu

(NJU CPL2024/ICS2024) SN EMUlator, a simple RV32IMAFD emulator for FUN and practice (JIT Mode WIP)

Language: C - Size: 3.57 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 4 - Forks: 0

Mr-Bossman/KISC-V

KISCV, a KISS principle riscv32i CPU

Language: Verilog - Size: 1.31 MB - Last synced at: 22 days ago - Pushed at: 4 months ago - Stars: 21 - Forks: 1

lupyuen/lora-sx1262

LoRa Driver for Semtech SX1262 on Apache NuttX OS, Linux (PineDio USB Adapter) and BL602 IoT SDK (PineDio Stack BL604)

Language: C - Size: 176 KB - Last synced at: 15 days ago - Pushed at: almost 3 years ago - Stars: 20 - Forks: 7

codeljo/riscv-bare-metal

RISC-V Bare Metal Starter Kit

Language: BitBake - Size: 149 KB - Last synced at: 2 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

ultraembedded/riscv32_linux_from_scratch

RISC-V 32-bit Linux From Scratch

Language: Makefile - Size: 9.77 KB - Last synced at: 20 days ago - Pushed at: almost 5 years ago - Stars: 32 - Forks: 5

AnthonyBSong/nanoForge

A assembler and instruction set simulator that supports a minimal set of instructions in various RISC languages.

Language: C++ - Size: 1.08 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 0

lupyuen/st7789-nuttx

ST7789 and LVGL Demo for Apache NuttX RTOS

Size: 325 KB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 1

Zilleali/RISCV

Language: C - Size: 4.88 KB - Last synced at: about 1 month ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

Elkeid-me/Xenon 📦

Xenon compiles SysY (a subset of C) to Koopa IR.

Language: Rust - Size: 133 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

ic-lab-duth/DRIM

DUTH RISC-V Microprocessor

Language: SystemVerilog - Size: 396 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 19 - Forks: 7

mk314k/AssemblyTS

Easy running and debugging for assembly codes, built using typescript

Language: TypeScript - Size: 601 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 5 - Forks: 0

jasonlin316/RISC-V-CPU

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

Language: Verilog - Size: 20.2 MB - Last synced at: 5 months ago - Pushed at: over 5 years ago - Stars: 119 - Forks: 27

jcdubois/xvisor-next Fork of avpatel/xvisor-next

eXtensible Versatile hypervISOR

Language: C - Size: 21.5 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

qubeck78/tangerineSDL

tangerine Risc-V SOC emulator for SDL ( PC, Linux, Webassembly ), includes RISC-V 32 IM emulation.

Language: JavaScript - Size: 56.7 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

lupyuen/zig-bl602-nuttx

Zig on RISC-V BL602 with Apache NuttX RTOS and LoRaWAN

Language: Zig - Size: 795 KB - Last synced at: 15 days ago - Pushed at: over 2 years ago - Stars: 35 - Forks: 2

lupyuen/bme280-nuttx

Apache NuttX Driver for Bosch BME280 I2C Sensor (Temperature + Humidity + Air Pressure) ported from Zephyr OS

Language: C - Size: 91.8 KB - Last synced at: 22 days ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 0

JN513/Baby-Risco-5

Multi-cycle RISC-V processor with RV32E implementation

Language: Tcl - Size: 1.2 MB - Last synced at: 24 days ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

JN513/Risco-5

Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.

Language: Verilog - Size: 3.49 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 15 - Forks: 1

JN513/Risco-5S

RISC-V Simulator with RV32IM implementation, built during a few days off.

Language: C - Size: 656 KB - Last synced at: 24 days ago - Pushed at: 6 months ago - Stars: 4 - Forks: 0

SpencerTorres/Click-V

A RISC-V emulator built with ClickHouse SQL

Language: Go - Size: 35.2 KB - Last synced at: about 2 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0

JN513/Pequeno-Risco-5

Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.

Language: Verilog - Size: 340 KB - Last synced at: 24 days ago - Pushed at: about 1 year ago - Stars: 6 - Forks: 0

muhammadtalhasami/riscv-assembly

This repo is the learning journey of the riscv assembly language. you will learn how to write the high level code in to the riscv assembly code.

Language: Assembly - Size: 10.7 KB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

mmxsrup/riscv-processor

RV32I Single Cycle Processor (CPU)

Language: SystemVerilog - Size: 52.7 KB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 10 - Forks: 2

lupyuen3/blockly-zig-nuttx Fork of google/blockly

Visual Programming for Zig with NuttX Sensors

Language: JavaScript - Size: 117 MB - Last synced at: 8 months ago - Pushed at: over 2 years ago - Stars: 23 - Forks: 1

vSasakiv/RV32I_Processor

Risc-V 32i processor written in the Verilog HDL

Language: Verilog - Size: 6.61 MB - Last synced at: 6 months ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 0

yaram/basic-riscv-verilog

Language: SystemVerilog - Size: 152 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

CosecSecCot/RISCV32I-Assembler

A custom Assembler for RISCV32I ISA

Language: C++ - Size: 82 KB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

SaiManojGubbala/RISC

Emulating a 32 Bit Risc-V Cpu in C Programming Language

Language: C - Size: 21.5 KB - Last synced at: 9 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

tisiphonee/Computer-Architecture-Course-Projects

Fixed-point dividers and RISC-V processors in various configurations. Features detailed overviews, functionality explanations, and example test cases for each project.

Language: Verilog - Size: 4.55 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0