Computer-Architecture-Course-Projects

Fixed-point dividers and RISC-V processors in various configurations. Features detailed overviews, functionality explanations, and example test cases for each project.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/tisiphonee%2FComputer-Architecture-Course-Projects

Stars: 0
Forks: 0
Open issues: 0

License: None
Language: Verilog
Size: 4.55 MB
Dependencies parsed at: Pending

Created at: about 1 year ago
Updated at: 9 months ago
Pushed at: 9 months ago
Last synced at: 9 months ago

Topics: devider, riscv, riscv32, verilog

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GitHub / tisiphonee / Computer-Architecture-Course-Projects