GitHub topics: pipeline-processor

Repositories

gchq/stroom

Stroom is a highly scalable data storage, processing and analysis platform.

Language: Java - Size: 190 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 447 - Forks: 61

danielklecha/PipelineBlocks

A .NET Standard library that can be used to create two-directional pipeline blocks.

Language: C# - Size: 2.52 MB - Last synced at: 3 days ago - Pushed at: 27 days ago - Stars: 0 - Forks: 0

pypyr/pypyr

pypyr task-runner cli & api for automation pipelines. Automate anything by combining commands, different scripts in different languages & applications into one pipeline process.

Language: Python - Size: 1.32 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 626 - Forks: 27

brunocampos01/organizacao-e-arquitetura-de-computadores

Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).

Language: Assembly - Size: 54.3 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 18 - Forks: 1

ultraembedded/riscv

RISC-V CPU Core (RV32IM)

Language: Verilog - Size: 5.27 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 1,398 - Forks: 251

phillbush/legv8

LEGv8 CPU implementation and some tools like a LEGv8 assembler

Language: Verilog - Size: 124 KB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 29 - Forks: 6

arhamhashmi01/rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Language: Verilog - Size: 357 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 10 - Forks: 0

cjrh/excitertools

itertools (and more-itertools) in the form of function call chaining (fluent interface)

Language: Python - Size: 264 KB - Last synced at: 8 days ago - Pushed at: 5 months ago - Stars: 14 - Forks: 2

evanalulu/RISC-V-Pipelined-Processor-Hazard-Unit

A 5-stage RISC-V pipelined processor with a Hazard Unit, designed to handle data, memory, and control hazards automatically. Features include register forwarding, pipeline stalling, and flushing for efficient execution of complex RISC-V programs without manual nop instructions.

Language: Assembly - Size: 56.6 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Khallil973/RV32I-Core

RV32I 5-Stage Pipelined CPU

Language: Verilog - Size: 218 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

z1skgr/VHDL-processor-CHARIS

Architecture of processor designed in vhdl

Language: VHDL - Size: 16.4 MB - Last synced at: 4 months ago - Pushed at: 7 months ago - Stars: 2 - Forks: 0

Blacksujit/Problems-I-have-Faced-In-My-Journey-OF-Programming

This repository contains the issues and errors which i have faced in my Prgramming and Machine Learning and Deep learning Journey

Language: Jupyter Notebook - Size: 11 MB - Last synced at: 3 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

RISCeirb/Risc-v-processor

Processor RISC-V and application

Language: C - Size: 2.43 MB - Last synced at: 4 days ago - Pushed at: 10 months ago - Stars: 1 - Forks: 1

muhammadtalhasami/RV32I_Single_Cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Language: Verilog - Size: 168 KB - Last synced at: about 2 months ago - Pushed at: 11 months ago - Stars: 3 - Forks: 0

sdasgup3/parallel-processor-design

Super scalar Processor design

Language: Verilog - Size: 137 KB - Last synced at: 3 months ago - Pushed at: almost 11 years ago - Stars: 21 - Forks: 3

Aayush-Bhargav/MIPS-Processor-Design

This repository consists of Python codes for implementation of MIPS Pipelined processor and Non-Pipelined processor

Language: Python - Size: 402 KB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Kushwanthchitipotu/computer-architecture-

This repository contains some of the codes that are used to understand computer architecture in c language

Language: C - Size: 254 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

saantiaguilera/go-pipeline

Build, execute and represent pipelines (aka workflows / templates) in Go

Language: Go - Size: 327 KB - Last synced at: 2 months ago - Pushed at: about 3 years ago - Stars: 28 - Forks: 2

BrosnanYuen/MIPS_Processor

16-bit MIPS Processor from scratch in VHDL

Language: VHDL - Size: 358 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

0mega28/CPU-Simulator

CENOS: The Modern CPU Simulator

Language: C++ - Size: 95.7 KB - Last synced at: 24 days ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 1

KASIRGA-KIZIL/tekno-kizil

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Language: Verilog - Size: 1.04 GB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 139 - Forks: 11

aman-nidhi/CSF342-Computer-Architecture

MIPS32 Assembly, Sorting Example in MIPS32 Assembly, CS-F342-Computer-Architecture-Lab

Language: Assembly - Size: 8.76 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 13 - Forks: 2

pypyr/pypyr-go-example

example project for golang using a ci devops container pipeline runner for build, test and deploy

Language: Go - Size: 12.7 KB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0

pypyr/pypyr-docker-img

Official docker images for pypyr and pypyr plug-ins

Language: Dockerfile - Size: 176 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 1

Armatiek/xslweb

Web application framework for XSLT and XQuery developers

Language: JavaScript - Size: 15.3 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 43 - Forks: 4

lsjbh45/processor-design

Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)

Language: SystemVerilog - Size: 195 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

kejriwalrahul/3-Stage-Pipeline

A Three Stage Pipeline 16-bit processor implemented in Verilog

Language: Verilog - Size: 445 KB - Last synced at: about 1 month ago - Pushed at: over 8 years ago - Stars: 4 - Forks: 3

wwoods/job_stream

An MPI-based C++ or Python library for easy distributed pipeline processing

Language: C++ - Size: 6.9 MB - Last synced at: about 4 hours ago - Pushed at: almost 7 years ago - Stars: 33 - Forks: 5

jamesminardi/mips-pipeline-processor

Hardware-Scheduled Pipeline Processor in VHDL

Language: Assembly - Size: 41.2 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

pypyr/pypyr-example

pypyr pipeline runner cli examples

Language: Python - Size: 114 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 12 - Forks: 0

CSpyridakis/Tomasulo 📦

Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm

Language: VHDL - Size: 8.29 MB - Last synced at: 4 days ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 1

apsknight/pipeliner

A Program to detect and resolve data-dependency in an assembly program.

Language: C++ - Size: 74.2 KB - Last synced at: 23 days ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 0

dapper-data/dapper-orchestrator

Orchestrate some data pipelines

Language: Go - Size: 74.2 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Solasel/WIOM

The WIOM: A RV32IM In-Order pipelined cpu with no cache and a naive branch predictor.

Language: C - Size: 286 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

CG-R8/APEX-assembly-pipeline-processor

Language: HTML - Size: 123 KB - Last synced at: over 1 year ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

preetam25/Six-Stage-Pipelined-Processor

IITB-RISC is a six stage pipelined processor described in VHDL and implemented on an FPGA

Language: VHDL - Size: 3.71 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 1

tanyagupta1/RISC-V-Simulator

A cycle-accurate simulator of a 5-stage RISC-V CPU pipeline, that supports stalling and forwarding

Language: Jupyter Notebook - Size: 149 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

viniciosbarretos/Pipeline-Simulator

Simulates execution of an assembly code in a pipeline

Language: Python - Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

TheLeopardsH/RISC-V-5-stage-pipelined-in-verilog

RISC-V-5 stage pipelined in verilog

Language: Verilog - Size: 4.81 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 1

mtzor/PipelineProcessor

This is a basic pipeline processor implemented in VHDL

Language: VHDL - Size: 607 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

JungleEngine/Project_ARCH_2

Simplified implementation of MIPS pipelined processor

Language: VHDL - Size: 272 KB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

adityagupta1089/Functional-Simulator-For-Simple-RISC

Functional/Pipeline Simulator for simpleRISC processor

Language: C - Size: 128 KB - Last synced at: almost 2 years ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

jbenden/deployer

Anywhere Local+CI+CD Made Easy!

Language: Python - Size: 133 KB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 0

RandyDeng/PipelinedArchitecture

A 5-Stage Pipelined Computer Architecture Simulator of LC3bsim in C

Language: C - Size: 10.7 KB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

adamlkl/Computer-Architecture-II

Language: C++ - Size: 16.3 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

FatemehFathi/multicycle-processor

Design and implementation of a multi-cycle processor

Language: Verilog - Size: 2.93 KB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0

udeyrishi/pipe

Android library for building pipelines for executing background tasks

Language: Kotlin - Size: 8.64 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 1

djzenma/RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

Language: Verilog - Size: 3.19 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 11 - Forks: 2

strongwong/bittyCore_RISC-V

This is a bitty CPU core of risc-v architecture, which is currently under development.

Language: Verilog - Size: 1.3 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 3

samkenxstream/SamKenX_public-datasets-pipelines Fork of GoogleCloudPlatform/public-datasets-pipelines

SamKenX Cloud-native, data onboarding architecture for Google Cloud Datasets

Language: Python - Size: 6.17 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

LeeChangYoon/Computer-Architecture

Repository for Computer Architecture class

Language: Assembly - Size: 43.4 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

zqzten/Pipelined-MIPS-CPU 📦

A Verilog implementation of a simplified pipelined MIPS CPU.

Language: Verilog - Size: 1.05 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

seanwu1105/mips-pipelined-processor 📦

Simulate the simple MIPS pipeline. Including structural, data and control hazard detection.

Language: Java - Size: 710 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 7 - Forks: 4

czim/laravel-processor

Pipelined processor framework for Laravel

Language: PHP - Size: 45.9 KB - Last synced at: 21 days ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0

TijsGroenendaal/DomainLine

Light weight request processing pipeline

Language: Java - Size: 19.5 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

levindoneto/MIPS

Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.

Size: 1.17 MB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 5 - Forks: 0

SM2A/Computer_Architecture_Course_Projects

🎓💻University of Tehran Computer Architecture Course Projects - Spring 2021

Language: Verilog - Size: 1.45 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

mohammadasim98/MIPS-Pipeline-Processor

A single cycle pipeline processor based on MIPS instruction set architecture (ISA)

Language: C - Size: 4.35 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

JoseDavidSS/CE_Architecture1.ASIP-Image_Interpolation Fork of juanignava/ComputerArchitecture1.Project2

Segundo proyecto para el curso de Arquitectura de Computadores. La idea es hacer un ASIP (Application Specific Set Processor) que genere interpolación de imagen por medio de un compilador, código en ensamblador, un procesador pipeline y scripts en alto nivel.

Language: Python - Size: 60.1 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0