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GitHub / ultraembedded / riscv

RISC-V CPU Core (RV32IM)

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ultraembedded%2Friscv

Stars: 1,080
Forks: 206
Open Issues: 14

License: bsd-3-clause
Language: Verilog
Repo Size: 5.27 MB
Dependencies: 0

Created: over 9 years ago
Updated: 22 days ago
Last pushed: over 2 years ago
Last synced: 21 days ago

Topics: asic, cpu, fpga, pipeline-processor, risc-v, riscv-linux, rv32i, rv32im, verification, verilator, verilog

Funding links: https://github.com/sponsors/ultraembedded

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