GitHub topics: vhdl-code

Repositories

TheGamingRogue/FPGA_Pong

Size: 0 Bytes - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

asazeez/COE608

COE608 Computer Organization and Architecture labs.

Language: VHDL - Size: 47 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

dannyvanderpol/nexys_a7_projects

Projects for the Nexys A7 FPGA development board

Language: Tcl - Size: 4.01 MB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 0 - Forks: 0

ElecGeek/MultiSignalGene

Generates multi channels sounds from primitives

Language: C++ - Size: 345 KB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 0 - Forks: 0

MateiB20/Proiect-n-echip-electronic-digital-

Counter– Registru Paralel

Language: Tcl - Size: 796 KB - Last synced at: 20 days ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

aidinattar/PMOD-FIR-filter-VHDL

Implementation of a FIR-filter on a FPGA and its employment in an audio system obtained using a PMOD I2S2.

Language: SystemVerilog - Size: 91.9 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 1

Choaib-ELMADI/getting-started-with-vhdl

Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.

Language: VHDL - Size: 38.5 MB - Last synced at: 3 days ago - Pushed at: 3 months ago - Stars: 7 - Forks: 0

ElecGeek/PulsesGene

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

Language: VHDL - Size: 180 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/working-with-fpga-and-vhdl

A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.

Language: VHDL - Size: 12.4 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 4 - Forks: 0

HMarchiori/relogio-xadrez-vhdl

Este projeto implementa um relógio de xadrez utilizando a linguagem VHDL. O sistema gerencia o tempo de jogo de dois jogadores e exibe os tempos restantes em um display.

Language: Tcl - Size: 8.79 KB - Last synced at: 2 days ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

BDSM-hardware/lock_handler

Manages multi points bondage locks, for self or collective bondage.

Language: PostScript - Size: 2.85 MB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 0

ClarkFieseln/FPGA_HW_SIM_FWK_2

FPGA Hardware Simulation Framework

Language: Python - Size: 820 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 22 - Forks: 1

Saradwata-Bandyopadhyay/VHDL_Codes_Forum

VHDL (VHSIC-HDL, Very High Speed Integrated Circuit Hardware Description Language) is a hardware description language. This is a dummy website built using Bootstrap, PHP and MySQL.

Language: PHP - Size: 1.19 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

Var7600/VHDL93-Docset

The VHDL93 Docset provides offline access to VHDL-93 documentation for users of Zeal and Dash. This docset includes syntax references, examples, and explanations of key VHDL concepts.

Language: HTML - Size: 268 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

Nyfeu/VHDL

This repository contains VHDL code and testbenches using GHDL, GTKWave, and Makefile.

Language: VHDL - Size: 91.8 KB - Last synced at: 19 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.

Language: C - Size: 6.94 MB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 8 - Forks: 1

Choaib-ELMADI/32-bit-processor-with-vhdl Fork of ZIKOAR/32-bit-processor-with-vhdl

Forked from ZIKOAR's 32-bit-processor-with-vhdl repository.

Language: VHDL - Size: 6.84 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

ZIKOAR/32-bit-processor-with-vhdl

A 32-bit VHDL processor with 26 instructions, including jumps, branches, and function calls. Implementing an FSM for execution control and testing using Quartus and ModelSim.

Language: VHDL - Size: 6.84 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 1

JN513/fpga_basics

Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog

Language: Verilog - Size: 59.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

DigitalDesignDen/open-scope-vhdl

Official repo of the open scope (a digital oscilloscope) developed by Digital Design Den

Language: VHDL - Size: 623 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

bryan-hoang/elec-271-digital-systems-labs 📦

VHDL Code for Labs done in a 2nd year engineering Digital Systems course (ELEC 271) at Queen's University.

Language: VHDL - Size: 10.7 KB - Last synced at: 4 days ago - Pushed at: 6 months ago - Stars: 3 - Forks: 1

VuxLoc/Digital_Design_With_VHDL

In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.

Size: 1000 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Alexandra07e/AC-secret

Arhitectura Calculatoarelor (VERILOG) - probleme rezolvate de mine (edaplayground flood)

Size: 1.95 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

mohammadamintahmasbi/AMA-Cach-RAM

Final project of VHDL lession, AMA Cach-RAM

Language: C - Size: 3.92 MB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

MohammedS2lah/Digital_Design_With_VHDL

In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.

Language: VHDL - Size: 36.1 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

akaeba/tinyUART

Lightweight UART core in VHDL

Language: VHDL - Size: 444 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 11 - Forks: 2

akaeba/eSpiMasterBfm

Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master

Language: VHDL - Size: 287 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 7 - Forks: 3

Var7600/VHDL-GENERATOR

App that Generate VHDL Code and Testbench template file

Language: HTML - Size: 7.15 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 0

Saeed-dev2/Saeed-dev2

Config files for my GitHub profile.

Size: 22.5 KB - Last synced at: 2 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

EngineerMichael/ModelSim-Altera-Project-Electronics-

⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.

Size: 25.4 KB - Last synced at: 4 months ago - Pushed at: 6 months ago - Stars: 3 - Forks: 0

Husseinabdo2003/Traffic_System

The project was about creating a traffic light system using microcontrollers and sensors using VHDL Programing Language. The FPGA used is basys 3, Ultrasonic sensor, DHT11 sensor, LCD, and a buzzer.

Size: 5.96 MB - Last synced at: 20 days ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

ClarkFieseln/FPGA_HW_SIM_FWK

FPGA Hardware Simulation Framework

Language: Python - Size: 2.18 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 15 - Forks: 2

romybompart/Basys3-clock-alarm-with-buzzer

Digital clock implemented in vhdl for the Basys 3 Board from Digilent.

Language: VHDL - Size: 177 KB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 0

dita-deb/VHDL_Labs

All labs from CPE 3020 compiled into one single repository -Anindita

Language: VHDL - Size: 79.1 KB - Last synced at: 21 days ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

el3ctrician/lfsr

A vhdl device to generate random numbers LFSR

Language: VHDL - Size: 2.93 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

HumbertoCG18/PUCRS-FSD-2.3-2023.24

Trabalhos, Projetos, Exercícios e aulas realizados em VHDL e Assembly na cadeira de Fundamentos de sistemas digitais, matéria do segundo semestre.

Language: VHDL - Size: 949 KB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

mazen-daghari/VHDL-AMS-Sonde

description d'un capteur ECG a base de VHDL-AMS (SIMPLORER V7)

Language: Brightscript - Size: 1.95 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

CodeNKoffee/clock-simulation

VHDL simulation of a digital clock for the CSEN605 course at the German University in Cairo. Includes clock generation and stimulus processes.

Language: VHDL - Size: 1000 Bytes - Last synced at: 8 days ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

arasgungore/256-colors-with-VGA

A VHDL-based VGA driver to display 256 different colors on a monitor.

Language: VHDL - Size: 492 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 14 - Forks: 0

Aom92/FPGA-Effects-Pedal

Proyecto de Tesis donde se realiza procesamiento digital de audio para hacer una pedalera de efectos de guitarra con la FPGA DE10-Lite

Language: Jupyter Notebook - Size: 210 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

seigtm/circuitry-spbpu-homework

This repository is dedicated to storing and managing homework assignments for the course "Digital Circuit Design: Modeling and Description Languages." The assignments primarily involve VHDL source code.

Language: VHDL - Size: 8.79 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

alirezakay/RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Language: VHDL - Size: 2.52 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 27 - Forks: 5

SaBuMa/Juego-Pong-en-VHDL--VHDL-Pong-Game

Juego Pong en VHDL // VHDL Pong-Game

Language: VHDL - Size: 32.9 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

SaBuMa/Procesador-en-VHDL-VHDL-Processor

VHDL Processor

Language: VHDL - Size: 2 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

Stavros/FSM_CarAlarm

Finite-State Machine Design of a Simple Car Security Alarm on FPGA

Language: VHDL - Size: 39.1 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

MuriloBarros304/lab-circuitos-digitais

Aplicações de Circuitos Digitais em VHDL

Language: VHDL - Size: 43.6 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

Prottasha19/adder-design

IC design with 8-bit adder.

Language: VHDL - Size: 11.7 KB - Last synced at: 10 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Charlie5DH/RISC-V-Single-Cycle-uP

Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture

Language: VHDL - Size: 82.2 MB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 11 - Forks: 1

rgeleon/VHDL_samples

Vhdl coursework

Language: VHDL - Size: 620 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

parsa-k/ALU-32bit

32-bit line ALU that can operate 24 functions, implemented in VHDL.

Language: VHDL - Size: 7.81 KB - Last synced at: 11 months ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 0

PoulamiSarkar24/VHDL

This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.

Language: VHDL - Size: 58.6 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

ITSUREN/ComputerArchitecture

🏛️ [RUSHED🏃‍♀️] A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for Academics.

Language: VHDL - Size: 707 KB - Last synced at: 3 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

Sadegh-Khedry/VHDL-Projects

This repository contains various VHDL projects showcasing digital logic circuits implemented using VHDL.

Language: C - Size: 1.25 MB - Last synced at: 1 day ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

rafidmuhammad/vhd-adder4

4-bit adder with outputs consists of sum and carry out

Language: VHDL - Size: 1.95 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

monicakarine/Pedagio

Projeto e simulação de um pedágio em VHDL para a disciplina de Laboratório de Sistemas Digitais da UFMG.

Language: VHDL - Size: 210 KB - Last synced at: 12 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

tocache/Altera-Cyclone-II-FPGA

Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II

Language: C - Size: 229 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 7 - Forks: 1

mongrelgem/cMIPS

A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

Language: Verilog - Size: 4.09 MB - Last synced at: 4 months ago - Pushed at: almost 6 years ago - Stars: 5 - Forks: 0

Erfangholiz/My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

Language: Verilog - Size: 383 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Elem404/Designing-and-Testing-Asynchronous-FIFO-Queues

Design and simulation for Asynchronous FIFO Queues in VHDL (with bacher's odd-even sort)

Language: VHDL - Size: 1.65 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

medamine101/VHDL_Bowling

Bowling Game in VHDL, the ._files are due to working on this project in both Windows and Linux systems

Language: VHDL - Size: 86.2 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

motcodes/VHDL-Code-Beispiele

HTBLuVA Salzburg VHDL code examples for Finals

Size: 4.38 MB - Last synced at: about 1 year ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

Alexdruso/Progetto-di-reti-logiche-2019

A VHDL project for the "Digital logic design" course 2020

Language: VHDL - Size: 9.28 MB - Last synced at: 2 months ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 0

kamplianitis/SingleCycleProcessor

Single cycle processor Design for the purposes of the course Computer Organisation at Technical University of Crete (TUC)

Language: VHDL - Size: 261 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 2

alessda/door_lock

Language: C - Size: 1.56 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

jagumiel/Data-Acquisition

This repository contains some examples of data acquisition over MATLAB, LabVIEW and VHDL.

Language: C - Size: 399 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

benitoss/ZXDOS

Spartan 6 Lx16 Xilinx FPGA board implementing retro 80's 90's machines

Language: VHDL - Size: 55.2 MB - Last synced at: about 2 months ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 0

Stavros/Multiplier4bit

A 4bit Multiplier in VHDL

Language: VHDL - Size: 2.94 MB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 1

tdurkut/BIL331

Bilgisayar Organizasyonu Verilog Projeleri

Language: Verilog - Size: 2.08 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0

pronoym99/PN-Sequence-Generator

This is a simulation based VHDL code developed in Xilinx to demonstrate a 4-bit PN sequence generator.

Language: C++ - Size: 2.38 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

AmelBENAIDA/Afficheur-7-segments-VHDL

Ce projet est un programme VHDL qui permet d'afficher les chiffres Hexadécimals (0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F)

Language: HTML - Size: 94.7 KB - Last synced at: about 1 year ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0

melanie-t27/Logic-Design-Project

Project for the Reti Logiche Course at @POLIMI, instructed by Prof. Gianluca Palermo during the academic year 2022/23

Language: VHDL - Size: 1.02 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

alialaei1/HDLab-FPGA-Development-Board

Open source FPGA development platform

Language: VHDL - Size: 21.6 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 46 - Forks: 22

CodiieSB/VHDL-4x1MUX

The VHDL code implements a 4x1 multiplexer (MUX), selecting one of four input signals based on the two select lines and producing a single output.

Language: VHDL - Size: 42 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-DFlipFlop

The VHDL code describes a D flip-flop with synchronous reset functionality.

Language: VHDL - Size: 31.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4Bit_UpDownCounter

A 4-bit up-down counter is a digital circuit capable of counting both upwards and downwards in binary, typically controlled by an up/down input signal.

Language: VHDL - Size: 41 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4Bit_UpCounter

A 4-bit up counter is a digital circuit that increments its output by one with each clock pulse, counting from 0000 to 1111 in binary, and resetting back to 0000 after reaching 1111.

Language: VHDL - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-2x4Decoder

The VHDL code implements a 2x4 decoder, converting two input signals into four output signals based on the input combinations.

Language: VHDL - Size: 40 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

MaksymAndreiev/CompEngineering

Workshop on the course "Methods and Technologies of Computer Engineering" at V. N. Karazin Kharkiv National University

Language: VHDL - Size: 9.77 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

GraceSevillano/RTIC-project-Antoine-s-army

This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed

Language: VHDL - Size: 12.3 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0