Erfangholiz/My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

Language: Verilog - Size: 383 KB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 0 - Forks: 0

Var7600/VHDL-GENERATOR

App that Generate VHDL Code and Testbench template file

Language: Java - Size: 7.04 MB - Last synced: 5 days ago - Pushed: 6 days ago - Stars: 4 - Forks: 0

ElecGeek/MultiSignalGene

Generates multi channels sounds from primitives

Language: C++ - Size: 247 KB - Last synced: 7 days ago - Pushed: 8 days ago - Stars: 0 - Forks: 0

Aom92/FPGA-Effects-Pedal

Proyecto de Tesis donde se realiza procesamiento digital de audio para hacer una pedalera de efectos de guitarra con la FPGA DE10-Lite

Language: VHDL - Size: 198 MB - Last synced: 13 days ago - Pushed: 13 days ago - Stars: 1 - Forks: 0

Elem404/Designing-and-Testing-Asynchronous-FIFO-Queues

Design and simulation for Asynchronous FIFO Queues in VHDL (with bacher's odd-even sort)

Language: VHDL - Size: 1.65 MB - Last synced: 25 days ago - Pushed: 25 days ago - Stars: 0 - Forks: 0

losfroger/timer-vhdl

Temporizador hecho con vhdl

Language: VHDL - Size: 12.7 KB - Last synced: about 1 month ago - Pushed: almost 5 years ago - Stars: 0 - Forks: 1

medamine101/VHDL_Bowling

Bowling Game in VHDL, the ._files are due to working on this project in both Windows and Linux systems

Language: VHDL - Size: 86.2 MB - Last synced: about 1 month ago - Pushed: 12 months ago - Stars: 0 - Forks: 0

motcodes/VHDL-Code-Beispiele

HTBLuVA Salzburg VHDL code examples for Finals

Size: 4.38 MB - Last synced: about 1 month ago - Pushed: about 5 years ago - Stars: 1 - Forks: 0

kamplianitis/SingleCycleProcessor

Single cycle processor Design for the purposes of the course Computer Organisation at Technical University of Crete (TUC)

Language: VHDL - Size: 261 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 2 - Forks: 2

alessda/door_lock

Language: C - Size: 1.56 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 1 - Forks: 0

jagumiel/Data-Acquisition

This repository contains some examples of data acquisition over MATLAB, LabVIEW and VHDL.

Language: C - Size: 399 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 2 - Forks: 0

tdurkut/BIL331

Bilgisayar Organizasyonu Verilog Projeleri

Language: Verilog - Size: 2.08 MB - Last synced: 2 months ago - Pushed: over 6 years ago - Stars: 0 - Forks: 0

pronoym99/PN-Sequence-Generator

This is a simulation based VHDL code developed in Xilinx to demonstrate a 4-bit PN sequence generator.

Language: C++ - Size: 2.38 MB - Last synced: 2 months ago - Pushed: over 5 years ago - Stars: 2 - Forks: 0

AmelBENAIDA/Afficheur-7-segments-VHDL

Ce projet est un programme VHDL qui permet d'afficher les chiffres Hexadécimals (0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F)

Language: HTML - Size: 94.7 KB - Last synced: 2 months ago - Pushed: about 6 years ago - Stars: 0 - Forks: 0

melanie-t27/Logic-Design-Project

Project for the Reti Logiche Course at @POLIMI, instructed by Prof. Gianluca Palermo during the academic year 2022/23

Language: VHDL - Size: 1.02 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

alialaei1/HDLab-FPGA-Development-Board

Open source FPGA development platform

Language: VHDL - Size: 21.6 MB - Last synced: 3 months ago - Pushed: 10 months ago - Stars: 46 - Forks: 22

CodiieSB/VHDL-4x1MUX

The VHDL code implements a 4x1 multiplexer (MUX), selecting one of four input signals based on the two select lines and producing a single output.

Language: VHDL - Size: 42 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-DFlipFlop

The VHDL code describes a D flip-flop with synchronous reset functionality.

Language: VHDL - Size: 31.3 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4Bit_UpDownCounter

A 4-bit up-down counter is a digital circuit capable of counting both upwards and downwards in binary, typically controlled by an up/down input signal.

Language: VHDL - Size: 41 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4Bit_UpCounter

A 4-bit up counter is a digital circuit that increments its output by one with each clock pulse, counting from 0000 to 1111 in binary, and resetting back to 0000 after reaching 1111.

Language: VHDL - Size: 39.1 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-2x4Decoder

The VHDL code implements a 2x4 decoder, converting two input signals into four output signals based on the input combinations.

Language: VHDL - Size: 40 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

MaksymAndreiev/CompEngineering

Workshop on the course "Methods and Technologies of Computer Engineering" at V. N. Karazin Kharkiv National University

Language: VHDL - Size: 9.77 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced: 25 days ago - Pushed: almost 6 years ago - Stars: 21 - Forks: 2

ElecGeek/PulsesGene

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

Language: PostScript - Size: 163 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

iremersin/HomeAutomation

Basic home automation process in VHDL.

Language: VHDL - Size: 2.93 KB - Last synced: 4 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

francescospangaro/ProgettoRL

Prova finale di Reti Logiche A.A. 2022/2023

Language: VHDL - Size: 5.33 MB - Last synced: about 1 month ago - Pushed: 12 months ago - Stars: 1 - Forks: 1

ArimondoScrivano/Progetto_Reti_Logiche 📦

progetto di Reti Logiche 2022/2023 del Politecnico di Milano

Language: VHDL - Size: 483 KB - Last synced: 4 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

Man2Dev/Hardware-Software-Codesign-course

Some of my Hardware Software Codesign projects

Language: C - Size: 2.4 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

onegentig/VUT-FIT-INP2022-projekt1 📦

První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Language: VHDL - Size: 2.42 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 0

onegentig/VUT-FIT-INC2022-projekt 📦

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

Language: VHDL - Size: 255 KB - Last synced: 4 months ago - Pushed: 5 months ago - Stars: 2 - Forks: 0

AzazHassankhan/VHDLCodeCraft

Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐

Size: 182 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 0

arxiver/Pipelined-MIPS

MIPS Pipelined CPU simulation using VHDL language

Language: VHDL - Size: 1.53 MB - Last synced: 6 days ago - Pushed: almost 4 years ago - Stars: 6 - Forks: 0

touunix/Keyboard-reading-PS-2-VHDL

Keyboard reading PS/2 VHDL | Odczyt klawiatury PS/2 VHDL

Language: VHDL - Size: 14.6 KB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

touunix/LED-display-control-VHDL

LED display control VHDL | Sterowanie wyświetlaczem LED VHDL

Language: VHDL - Size: 685 KB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 1 - Forks: 0

touunix/MUX-VHDL

MUX VHDL | Układ kombinacyjny VHDL

Language: VHDL - Size: 681 KB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 1 - Forks: 0

touunix/Simple-stopwatch-VHDL

Simple stopwatch VHDL | Prosty stoper VHDL

Language: VHDL - Size: 677 KB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 1 - Forks: 0

touunix/Johnson-code-counter-VHDL

Johnson code counter VHDL | Licznik w kodzie Johnsona VHDL

Language: VHDL - Size: 496 KB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 2 - Forks: 0

touunix/RS-232-standard-handling-VHDL

RS-232 standard handling VHDL | Obsługa portu RS-232

Language: VHDL - Size: 9.77 KB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 2 - Forks: 0

touunix/Gray-code-counter-VHDL

Gray code counter VHDL | Licznik w kodzie Graya VHDL

Language: VHDL - Size: 499 KB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 1 - Forks: 0

touunix/Frequency-divider-VHDL

Frequency divider VHDL | Dzielnik częstotliwości VHDL

Language: VHDL - Size: 481 KB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 1 - Forks: 0

talhasevinc/FPGA

FPGA Digital Hardware Design

Language: VHDL - Size: 74.5 MB - Last synced: 24 days ago - Pushed: about 2 years ago - Stars: 3 - Forks: 0

DanielSouzaBertoldi/vhdl

Este projeto foi feito para a disciplina de Laboratório de Arquitetura de Computadores, e tem como objetivo implementar um MIPS simplificado utilizando-se da linguagem VHDL. As instruções implementadas para o microprocessador são: ADD, ADDI, SUB, LW, SW, BEQ, BNE, JAL, J, SLT, AND, OR, JR, SLL, SRL

Language: VHDL - Size: 5.28 MB - Last synced: 6 months ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 1

aybaras/VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

Language: VHDL - Size: 494 KB - Last synced: 4 months ago - Pushed: almost 2 years ago - Stars: 6 - Forks: 2

mariateodorapopescu/vhdl_fsm

A team-project about a fem vending-machine I had in 2nd year of uni

Language: VHDL - Size: 10.7 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

HumbertoCG18/PUCRS-Fundamentos-Sistemas-Digitais-2-2023

Trabalhos, Projetos, Exercícios e aulas realizados em VHDL na cadeira de Fundamentos de sistemas digitais, matéria do segundo semestre.

Language: VHDL - Size: 385 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 1 - Forks: 0

Ad-Vi/dino-led

Dino-chrome project on a 7*5 LED Matrix in VHDL

Language: VHDL - Size: 11.9 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

ads930/Thermostat

This is the code for the multiple implementations of a finite state machine thermostat. There is an implementation in C for the dsPIC33EP64MC502, an implementation with VHDL, and an implementation with LabVIEW and DAQmx. TwithFPO_DAQmx.vi requires a MyDAQ to run the program.

Language: C - Size: 82 KB - Last synced: 7 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

Kazhuu/audio-synthesizer

Copy of old FPGA audio synthesizer project for DE2 development board

Language: VHDL - Size: 4.76 MB - Last synced: 25 days ago - Pushed: over 5 years ago - Stars: 8 - Forks: 0

mostafapiran/VHDL-for-FPGA

My projects in VHDL language for FPGA in Modelsim software

Language: VHDL - Size: 11.4 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 0 - Forks: 0

seigtm/circuitry-spbpu-homework

This repository is dedicated to storing and managing homework assignments for the course "Digital Circuit Design: Modeling and Description Languages." The assignments primarily involve VHDL source code.

Language: VHDL - Size: 8.79 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

pratikbhuran/Up_Counter

VHDL implementation of Up counter.

Language: VHDL - Size: 13.7 KB - Last synced: 7 months ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0

santifs/simon-game-vhdl

VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.

Language: VHDL - Size: 7.94 MB - Last synced: 7 months ago - Pushed: over 3 years ago - Stars: 3 - Forks: 1

santifs/ultrasonic-sensor

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

Language: VHDL - Size: 6.83 MB - Last synced: 7 months ago - Pushed: over 4 years ago - Stars: 8 - Forks: 2

Subhankar2000/Xilinx-ISE-8.2i-EC792-VLSI-LAB

saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)

Language: VHDL - Size: 13.8 MB - Last synced: 7 months ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0

shahjui2000/Push-Button-Door-VHDL-

Simulation of a push button door lock with a variable password

Size: 160 KB - Last synced: 7 months ago - Pushed: over 4 years ago - Stars: 2 - Forks: 1

SamsonAdem/HW_SW_Co_Design_FPGA

Hardware accelerator for Image processing in FPGA

Language: C++ - Size: 41.7 MB - Last synced: 4 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

aliansgp/VHDL_Multipliers

Different Multipliers code in VHDL and Comparison

Language: C - Size: 1.35 MB - Last synced: 8 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

aliansgp/VHDL_Adders

Different adders code in VHDL and Comparison

Language: C - Size: 1.3 MB - Last synced: 8 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

Glock-Atom/Adder-Project

Language: VHDL - Size: 9.77 KB - Last synced: 8 months ago - Pushed: over 2 years ago - Stars: 1 - Forks: 0

Glock-Atom/VHDL-Multiplexer

Language: VHDL - Size: 4.88 KB - Last synced: 8 months ago - Pushed: over 2 years ago - Stars: 1 - Forks: 0

mrtkp9993/VHDLExamples

VHDL examples.

Language: VHDL - Size: 39.1 KB - Last synced: 25 days ago - Pushed: over 3 years ago - Stars: 8 - Forks: 0

aniekanBane/poly-eval-vhdl

Modelling and simulation of a polynomial evaluator in VHDL using stepwise refinement.

Language: VHDL - Size: 32.2 KB - Last synced: 9 months ago - Pushed: about 3 years ago - Stars: 1 - Forks: 0

josefdc/Laboratorio-Fundamentos-De-Electronica

Este repositorio es el hogar del curso de Fundamentos de Electrónica de la Universidad Tecnológica de Pereira. Aquí, los estudiantes y profesores pueden colaborar en el desarrollo y mejora continua del curso, compartiendo materiales didácticos, ejercicios prácticos, proyectos y más.

Language: VHDL - Size: 222 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

DericAugusto/ISN2023_DigitalSystems

Material from the course of Design of Digital Systems at ENSEM - Université de Lorraine.

Language: VHDL - Size: 40.8 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

abdalla1912mohamed/-AES-encryption-and-decryption-platform-in-FPGA-communication

implementing a protected communication platform between 2 FPGA's. Data is entered through a keyboard-FPGA interface then the data is encrypted using AES encryption and sent to the second FPGA where the decryption occurs if the decryption key is given and the data is displayed using an FPGA-LCD interface using VHDL scripts

Language: C - Size: 1.14 MB - Last synced: 9 months ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0

hk-117/VHDL

Some example of vhdl code, using ghdl and gtkwave.

Language: VHDL - Size: 30.3 KB - Last synced: 9 months ago - Pushed: about 1 year ago - Stars: 1 - Forks: 0

mtzor/PipelineProcessor

This is a basic pipeline processor implemented in VHDL

Language: VHDL - Size: 607 KB - Last synced: 9 months ago - Pushed: almost 2 years ago - Stars: 1 - Forks: 0

eimon96/VHDL

Language: VHDL - Size: 342 KB - Last synced: 9 months ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0

farbodfld/CoDesign-Course

Projects of CoDesign course at SBU

Language: VHDL - Size: 3.86 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 1 - Forks: 0

qzxtu/Basys3MusicNotes

A VHDL code that produces 8 musical notes (do, re, mi, fa, sol, la, si and do-8va) in Basys 3, one for each switch.

Language: Tcl - Size: 10.7 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

Stavros/Multiplier4bit

A 4bit Multiplier in VHDL

Language: VHDL - Size: 2.94 MB - Last synced: 10 months ago - Pushed: over 4 years ago - Stars: 2 - Forks: 1

Stavros/LedToggle

An example for NIOS II processor to toggle a Led with a Button

Language: Verilog - Size: 13.2 MB - Last synced: 10 months ago - Pushed: over 1 year ago - Stars: 2 - Forks: 1

Stavros/FSM_CarAlarm

Finite-State Machine Design of a Simple Car Security Alarm on FPGA

Language: VHDL - Size: 39.1 KB - Last synced: 10 months ago - Pushed: over 4 years ago - Stars: 4 - Forks: 0

Stavros/4bitCounterParLoad

A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder

Language: VHDL - Size: 3.11 MB - Last synced: 10 months ago - Pushed: over 4 years ago - Stars: 2 - Forks: 0

tristan-oa/ALU-in-VHDL

Building an ALU using VHDL

Size: 5.21 MB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 1 - Forks: 0

berkaybarlas/VHDL-Clock-Project

⏰ A Fully Functional Clock with alarm and snooze .

Language: VHDL - Size: 7.81 KB - Last synced: 10 months ago - Pushed: over 6 years ago - Stars: 3 - Forks: 2

Megapiro/Progetto-RETI-2019

Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - a.a. 2018-2019

Language: VHDL - Size: 323 KB - Last synced: 11 months ago - Pushed: about 4 years ago - Stars: 3 - Forks: 3

DavidRosero/FPGAWorldCodes

Ejemplos de codigo con implementación en hardware para la tarjeta Cyclone IV lenguaje VHDL

Language: VHDL - Size: 382 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 2

Steve-Teal/pumpkin-cpu

A small general purpose, scalable, 16-bit, 16 instruction CPU core written in VHDL

Language: C - Size: 83 KB - Last synced: 11 months ago - Pushed: over 3 years ago - Stars: 4 - Forks: 0

lorenzozaccomer/iterative-multiplier

Project for Electronic Calculators course.

Language: VHDL - Size: 4.77 MB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 0 - Forks: 0

elbekka/Programacion-De-Hardware-VHDL

4 bits ALU with 2 entries of selection using structural vhdl

Language: VHDL - Size: 4.88 KB - Last synced: 5 months ago - Pushed: almost 6 years ago - Stars: 7 - Forks: 1

abdelazeem201/Arm-Core

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.

Language: C - Size: 6.94 MB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 4 - Forks: 2

Bryce-Leung/FPGA-UART-Protocol

UART Protocol made for Altera DE2-115 FPGA in VHDL

Language: VHDL - Size: 46.9 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 1

AliceO2Group/alice-fit-fpga

ALICE Fast Interaction Trigger (FIT) FPGA code

Language: VHDL - Size: 32.2 MB - Last synced: 6 days ago - Pushed: 7 months ago - Stars: 5 - Forks: 4

IgnacioChirinos/MIPS-VHDL-Vivado

MIPS processor that performs matrix multiplication 3x3 based on VHDL and implemented in XILINX

Language: VHDL - Size: 296 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 1 - Forks: 0

ClarkFieseln/FPGA_HW_SIM_FWK_2

FPGA Hardware Simulation Framework

Language: Python - Size: 820 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 10 - Forks: 0

HuzaifaElahi/Space-Invaders

Language: VHDL - Size: 7.81 KB - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 1 - Forks: 0

LucaLombardini/fft_sylvester_ii

Development and Testing of an Hardware achitecture dedicate to the FFT calculus based on Cooley-Tuckey's Algorithm

Language: VHDL - Size: 9.57 MB - Last synced: 4 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

Suvraneel/VHDL-Xilinx

Projects were generated in Xilinx v14.7 If you're using Xilinx you may simply import the projects. Otherwise just read the codes in .vhd extensioned files. ☮️

Language: C - Size: 9.47 MB - Last synced: about 1 month ago - Pushed: about 2 years ago - Stars: 2 - Forks: 0

datacipy/VHDL

Příklady ke knize Data, čipy, procesory

Language: VHDL - Size: 29 MB - Last synced: 12 months ago - Pushed: over 3 years ago - Stars: 16 - Forks: 3

ClarkFieseln/FPGA_HW_SIM_FWK

FPGA Hardware Simulation Framework

Language: Python - Size: 2.18 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 12 - Forks: 1

Tanmaymundra/vhdl

This repository contains example of logic such as comparator, encoder, etc in vhdl. Feel Free to add other examples in this repository

Language: VHDL - Size: 76.2 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 2 - Forks: 0

Sanchit-20/Ten_Bit_Multiplier

Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.

Language: VHDL - Size: 777 KB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 2 - Forks: 0

mustafa1728/Digital-Image-Filtering-VHDL

A VHDL description of a digital image filtering system on FPGAs. Part of COL215 course project.

Language: VHDL - Size: 3.3 MB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 1 - Forks: 0

Saradwata-Bandyopadhyay/VHDL_Codes_Forum

VHDL (VHSIC-HDL, Very High Speed Integrated Circuit Hardware Description Language) is a hardware description language. This is a dummy website built using Bootstrap, PHP and MySQL.

Language: PHP - Size: 213 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 2 - Forks: 0

tertiarycourses/FPGATraining

Exercise files for VHDL Programming Training for FPGA

Language: VHDL - Size: 6.84 KB - Last synced: about 1 year ago - Pushed: almost 6 years ago - Stars: 3 - Forks: 0

JCLArriaga5/8-bit-counter_VHDL

Arquitectura en VHDL de un contador de 8 bits

Language: VHDL - Size: 1000 Bytes - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 1 - Forks: 0

tocache/Altera-Cyclone-II-FPGA

Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II

Language: C - Size: 229 MB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 5 - Forks: 1

soumyadip007/VHDL-Modelsim-Altera-Simulator-COA

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

Size: 78.1 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 4 - Forks: 1

Alexdruso/Progetto-di-reti-logiche-2019

A VHDL project for the "Digital logic design" course 2020

Language: VHDL - Size: 9.28 MB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 3 - Forks: 0