GitHub topics: half-adder
mcquerol/electronic-systems
Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.
Size: 8.95 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 2 - Forks: 0
VarshithGovi/Half-Adder-Design-Verilog
A compact Verilog project implementing a half-adder with gate-level modeling, featuring a detailed testbench for functional verification and simulation.
Language: Verilog - Size: 23.4 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
bespoyasov/binary-full-adder-in-the-game-of-life
Binary adder implementation in the Game of Life written in JavaScript using canvas.
Language: JavaScript - Size: 199 KB - Last synced at: 14 days ago - Pushed at: 3 months ago - Stars: 6 - Forks: 1
daedalus/bitlogicemu 📦
bitwise operation examples
Language: Python - Size: 15.6 KB - Last synced at: 25 days ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1
shane-staret/TwosComplementer
A Java program that converts a binary number into it's two's complement equivalent. This is used within the SimpleBinaryCalculator repository.
Language: Java - Size: 8.79 KB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 0 - Forks: 1
shane-staret/SimpleBinaryCalculator
A Java binary calculator based on a system of gates
Language: Java - Size: 24.4 KB - Last synced at: about 1 month ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 1
Zannatul-Naim/Digital-System-Design
Digital System Design Lab Codes using Verilog
Language: Verilog - Size: 52.7 KB - Last synced at: 2 months ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
PoulamiSarkar24/VHDL
This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.
Language: VHDL - Size: 58.6 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
ichko/nand-to-tetris
This repository contains HWs and material from the nand to tetris course
Language: Assembly - Size: 873 KB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 1
krish1925/Logic-Design-Verilog
Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module
Language: Tcl - Size: 8.53 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Stavros/Multiplier4bit
A 4bit Multiplier in VHDL
Language: VHDL - Size: 2.94 MB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 1
ginf-ch/digitaltechnik-skript
Skript zur Einführung in die Digitaltechnik
Language: TeX - Size: 12.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
joeymaillette04/VHDL
VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design
Language: VHDL - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
nxbyte/Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Language: Verilog - Size: 2.23 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 91 - Forks: 21
aliansgp/VHDL_Adders
Different adders code in VHDL and Comparison
Language: C - Size: 1.3 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
imvickykumar999/Logical-Redstone-Reloaded
Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/
Language: Python - Size: 128 MB - Last synced at: 29 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1
newajsharif91/Verilog_HDL_Digital-System-Design
CSE-2112 Digital Syatem Design LAb
Language: Verilog - Size: 6.84 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
DatDarkAlpaca/dat-emulation-sandbox
A simulation where I can connect virtual logic gates and build virtual CIs.
Language: C++ - Size: 60.5 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
scriptographers/CS254-Assignment-3
Assignment 3, Digital Logic Design Lab, Spring 2021, IIT Bombay
Language: VHDL - Size: 1.03 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0
jgesc/VerilogTests
A repository for some modules I made while learning Verilog
Language: Verilog - Size: 10.7 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0
rahul21316/verilog-adders
All the various adders in Verilog!
Size: 22.5 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0
Grv-Singh/Digital-Systems-Design
Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦
Language: MATLAB - Size: 3.24 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
senavs/BitJoy
:heavy_check_mark: Bit, Bytes and Logical Gates Abstraction
Language: Python - Size: 31.3 KB - Last synced at: 3 days ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0
